Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Recent Progress on Flexible Room-Temperature Gas Sensors Based on Metal Oxide Semiconductor

With the rapid development of the Internet of Things,there is a great demand for portable gas sensors.Metal oxide semiconductors(MOS)are one of the most traditional and well-studied gas sensing materials and have been widely used to prepare various commercial gas sensors.However,it is limited by high operating temperature.The current research works are directed towards fabricating high-performance flexible room-temperature(FRT)gas sensors,which are effective in simplifying the structure of MOS-based sensors,reducing power consumption,and expanding the application of portable devices.This article presents the recent research progress of MOS-based FRT gas sensors in terms of sensing mechanism,performance,flexibility characteristics,and applications.This review comprehensively summarizes and discusses five types of MOS-based FRT gas sensors,including pristine MOS,noble metal nanoparticles modified MOS,organic polymers modified MOS,carbon-based materials(carbon nanotubes and graphene derivatives)modified MOS,and two-dimensional transition metal dichalcogenides materials modified MOS.The effect of light-illuminated to improve gas sensing performance is further discussed.Furthermore,the applications and future perspectives of FRT gas sensors are also discussed.

Structural evolution of low-dimensional metal oxide semiconductors under external stress

Metal oxide semiconductors(MOSs) are attractive candidates as functional parts and connections in nanodevices.Upon spatial dimensionality reduction, the ubiquitous strain encountered in physical reality may result in structural instability and thus degrade the performance of MOS. Hence, the basic insight into the structural evolutions of low-dimensional MOS is a prerequisite for extensive applications, which unfortunately remains largely unexplored. Herein, we review the recent progress regarding the mechanical deformation mechanisms in MOSs, such as CuO and ZnO nanowires(NWs). We report the phase transformation of CuO NWs resulting from oxygen vacancy migration under compressive stress and the tensile strain-induced phase transition in ZnO NWs. Moreover, the influence of electron beam irradiation on interpreting the mechanical behaviors is discussed.

Improved interfacial and electrical properties of GaSb metal oxide semiconductor devices passivated with acidic(NH_4)_2S solution

Surface passivation with acidic （NH4）2S solution is shown to be effective in improving the interfacial and electrical properties of HfOE/GaSb metal oxide semiconductor devices. Compared with control samples, the samples treated with acidic （NH4）2S solution show great improvements in gate leakage current, frequency dispersion, border trap density, and interface trap density. These improvements are attributed to the enhancing passivation of the substrates, according to analysis from the perspective of chemical mechanism, X-ray photoelectron spectroscopy, and high-resolution cross-sectional transmission electron microscopy.

Cu_2O-based solar cells using oxide semiconductors

We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO（AZO）/n-type oxide semiconductor/p-type Cu_2O heterojunction solar cells fabricated using p-type Cu_2O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu_2O sheets under various deposition conditions using a pulsed laser deposition method. In Cu_2O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa_2O_4 thin-film layer. In most of the Cu_2O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO–MgO and Ga_2O_3–Al_2O_3systems, higher conversion efficiencies（á/ as well as a high open circuit voltage（Voc/ were obtained by using a relatively small amount of MgO or Al_2O_3, e.g.,（ZnO）0：91–（MgO）0：09 and（Ga_2O_3/0：975–（Al_2O_3/0：025, respectively. When Cu_2O-based heterojunction solar cells were fabricated using Al_2O_3–Ga_2O_3–MgO–ZnO（AGMZO）multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high Vocof 0.98 V and an á of 4.82% were obtained. In addition, an enhanced á and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu_2O heterojunction solar cells fabricated using Na-doped Cu_2O（Cu_2O：Na） sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an á of 6.25% and a Vocof 0.84 V were obtained in a Mg F2/AZO/n-（Ga_2O_3–Al_2O_3//p-Cu_2O：Na heterojunction solar cell fabricated using a Cu_2O：Na sheet with a resistivity of approximately 10 cm and a（Ga_（0：975）A_（l0：025）/2O3 thin film with a thickness of approximately 60 nm.In addition, a Vocof 0.96 V and an á of 5.4% were obtained in a Mg F_2/AZO/n-AGMZO/p-Cu_2O：Na heterojunction solar cell.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors（TFTs）, fabricating with atomic layer deposition（ALD） processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types（directions）. The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.

Investigation of trap states in Al_2O_3 InAlN/GaN metal–oxide–semiconductor high-electron-mobility transistors

In this paper the trapping effects in Al2O3/In0.17Al0.83N/GaN MOS-HEMT（here, HEMT stands for high electron mobility transistor） are investigated by frequency-dependent capacitance and conductance analysis. The trap states are found at both the Al2O3/In AlN and InAlN/GaN interface. Trap states in InAlN/GaN heterostructure are determined to have mixed de-trapping mechanisms, emission, and tunneling. Part of the electrons captured in the trap states are likely to tunnel into the two-dimensional electron gas（2DEG） channel under serious band bending and stronger electric field peak caused by high Al content in the In AlN barrier, which explains the opposite voltage dependence of time constant and relation between the time constant and energy of the trap states.

X-ray irradiation-induced degradation in Hf_(0.5)Zr_(0.5)O_(2) fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors

The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were fabricated.The total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel devices.The short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold voltage.It was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel devices.Also,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried oxide.By extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was revealed.Finally,the split capacitance-voltage measurements were used to validate the analysis.

An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC

Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.

Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for Homogeneous MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

Metal oxide ion gated transistors based sensors

Metal oxide ion-gated transistors(MOIGTs)have garnered significant attention within the sensing domain due to their potential for achieving heightened sensitivity while consuming minimal energy across diverse scenarios.By harnessing the advantageous combination of metal oxides'high carrier mobility and facile surface customization,coupled with the potent signal amplification capabilities of ion-gated transistors,MOIGTs offer a promising avenue for discerning biomolecules,overseeing chemical reactions,p H levels,as well as facilitating gas or light determination.Over the past few decades,the MOIGT field has made remarkable strides in refining device physics,enhancing material properties,showcasing robust sensing capabilities,and broadening its application spectrum.These advancements have simultaneously unveiled new challenges and opportunities,necessitating interdisciplinary expertise to fully unlock the commercial potential of MOIGTs.In this comprehensive review,we offer a snapshot of this swiftly evolving technology,delve into its current applications,and provide insightful recommendations for future directions in the coming decade.

Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation

Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.

Proton induced radiation effect of SiC MOSFET under different bias

Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)induced by 20 MeV proton under drain bias(V_(D)=800 V,V_(G)=0 V),gate bias(V_(D)=0 V,V_(G)=10 V),turn-on bias(V_(D)=0.5 V,V_(G)=4 V)and static bias(V_(D)=0 V,V_(G)=0 V)are investigated.The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation.When the cumulative proton fluence reaches 2×10^(11)p·cm^(-2),the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left,and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious.In the deep level transient spectrum test,it is found that the defect energy level of SiC MOSFET is mainly the ON2(E_(c)-1.1 eV)defect center,and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most.By comparing the degradation of SiC MOSFET under proton cumulative irradiation,equivalent 1 MeV neutron irradiation and gamma irradiation,and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET,the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage.The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.

Simple point contact WO_3 sensor for NO_2 sensing and relevant impedance analysis

A simple and new point contact tungsten trioxide （WO3） sensor, which can be prepared by the oxidation of tungsten filaments via in-situ induction heating, likely detects low concentration （ppm level） environmental pollutants such as NO2. X-ray diffraction （XRD） and field emission scanning electron microscopy （FE-SEM） were applied to characterize the phase and the microstructure of the samples, respec-tively. It was found that the synthesized WO3 films exhibited a monoclinic phase and were composed of hierarchical microcrystals and nanocrystals. The point contact WO3 sensor （W-WO3-W） showed rectifying characteristics and an ideal sensing performance of about 110 C. A single semicircle in Nyquist plots was recorded by electrochemical impedance spectroscopy （EIS） at a relatively low temperature of 150 C but faded away above 200 C, which revealed that the sensing process was governed by a determining factor, i.e., grain boundaries at the contact site.

Abnormal oxidation in nickel silicide and nickel germanosilicide in sub-micro CMOS

After post-silicidation annealing at various temperatures for 30 min, abnormal oxidation and agglomeration in nickel silicide and nickel germanosilicide are investigated under different conditions of NiSi, with As-, In-, and Sb-doped Si substrates of nickel germanosilicide without any dopants. The NiSi thickness, dopant species, doping concentration, and silicide process conditions are dominant factors for abnormal oxidation and NiSi agglomeration. Larger dopants than Si, thinner NiSi thickness and SiGe suhstrates, and higher dopant concentrations promote abnormal oxidation and agglomeration.

Design of Power Amplifier for mm Wave 5G and Beyond

With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.

A 60 GHz Phased Array System Analysis and Its Phase Shifter in a 40 nm CMOS Technology

A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the receiver is improved with the beaming forming function.Therefore,the communication data rate and distance are improved accordingly.The phase shifter is the key component for achieving the beam forming function,and its resolution and power consumption are also very critical.In the second half of this paper,an analysis of phase shifter is introduced,and a 60 GHz 5 bit digitally controlled phase shifter in 40 nm complementary metal oxide semiconductor(CMOS)technology is presented.In this presented phase shifter,a hybrid structure is implemented for its advantage on lower phase deviation while keeping comparable loss.Meanwhile,this digitally controlled phase shifter is much more compact than other works.For all 32 states,the minimum phase error is 1.5°,and the maximum phase error is 6.8°.The measured insertion loss is-20.9±1 dB including pad loss at 60 GHz and the return loss is more than 10 dB over 57-64 GHz.The total chip size is 0.24 mm^2 with 0 mW DC power consumption.

Investigation of gate current in nano-scale MOSFETs by Monte Carlo solution of quantum Boltzmann equation

This paper investigates gate current through ultra-thin gate oxide of nano-scale metal oxide semiconductor field effect transistors （MOSFETs）, using two-dimensional （2D） full-band self-consistent ensemble Montc Carlo method based on solving quantum Boltzmann equation. Direct tunnelling, Fowler-Nordheim tunnelling and thermionic emission currents have been taken into account for the calculation of total gate current. The 2D effect on the gate current is investigated by including the details of the energy distribution for electron tunnelling through the barrier. In order to investigate the properties of nano scale MOSFETs, it is necessary to simulate gate tunnelling current in 2D including non-equilibrium transport.

Model of hot-carrier induced degradation in ultra-deep sub-micrometer nMOSFET

The degradation produced by hot carrier （HC） in ultra-deep sub-micron n-channel metal oxide semiconductor field effect transistor （nMOSFET） has been analyzed in this paper. The generation of negatively charged interface states is the predominant mechanism for the ultra-deep sub-micron nMOSFET. According to our lifetime model of p-channel MOFET （pMOFET） that was reported in a previous publication, a lifetime prediction model for nMOSFET is presented and the parameters in the model are extracted. For the first time, the lifetime models of nMOFET and pMOSFET are unified. In addition, the model can precisely predict the lifetime of the ultra-deep sub-micron nMOSFET and pMOSFET.