The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications.This paper deals with an implementation of the FFT on the accelerator system,a heterogeneous multi-core ar...The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications.This paper deals with an implementation of the FFT on the accelerator system,a heterogeneous multi-core architecture to accelerate computation-intensive parallel computing in scientific and engineering applications.The Engineering and Scientific Computation Accelerator (ESCA) consists of a control unit and a single instruction multiple data (SIMD) processing element (PE) array,in which PEs communicate with each other via a hierarchical two-level network-on-chip (NoC) with high bandwidth and low latency.We exploit the architecture features of ESCA to implement a parallel FFT algorithm efficiently.Experimental results show that both the proposed parallel FFT algorithm and the ESCA architecture are scalable.The 16-bit fixed-point parallel FFT performance of ESCA is compared with a published work to prove the superiority of the mapping algorithm and the hardware architecture.The floating-point parallel FFT performances of ESCA are evaluated and compared with those of the IBM Cell processor and GPU to demonstrate the computing power of the ESCA system for high performance applications.展开更多
The design of reconfigurable multi-butterfly parallel radix-r FFT (Fast Fourier Transform) processors is proposed. FFT is widely used in signal processing, and the application needs real-time and high performance, whi...The design of reconfigurable multi-butterfly parallel radix-r FFT (Fast Fourier Transform) processors is proposed. FFT is widely used in signal processing, and the application needs real-time and high performance, while most of the traditional designs are limited to the power of two, which wastes the buffers and multipliers in big data. In response to the problem, we improve the parallel FFT algorithm with the design of reconfigurable control machine combined with buffer/multiplier, and the cost function with the input of radix/number/paddling number/time consuming is deduced. Constrained with the number of buffer and multipliers, the radix and number can be computed with the optimum cost function, and the resolution space of computing performance and hardware cost is presented. The proposed guarantees the real-time performance with better flexibility compared with the previous literature, and the comparison also suggests the effectiveness of the design.展开更多
为解决并行应用程序使用FFTW(Fastest Fourier Transform in the West)并行软件包所面临的计算规模难以扩展、数据结构变动大、实现不同数据结构间通信难度大、接口不确定等问题,在JASMIN框架内设计实现FFT并行解法器.该解法器封装了数...为解决并行应用程序使用FFTW(Fastest Fourier Transform in the West)并行软件包所面临的计算规模难以扩展、数据结构变动大、实现不同数据结构间通信难度大、接口不确定等问题,在JASMIN框架内设计实现FFT并行解法器.该解法器封装了数据分布存储、数据通信等并行计算细节,通过重新分布存储数据,调用一维FFT变换实现高维FFT的并行计算,并提供规范接口,支撑用户简便地实现FFT的并行计算.数值测试表明,该解法器具有很好的并行性能.该解法器已应用于激光等离子体成丝不稳定性的数值模拟并行程序,它在2048个处理器上的并行效率可达80%以上.展开更多
基金Project supported by the National Natural Science Foundation of China (Nos.60973035 and 60976027)the Natural Science Foundation of Hubei Province,China (No.2010CDB02705)
文摘The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications.This paper deals with an implementation of the FFT on the accelerator system,a heterogeneous multi-core architecture to accelerate computation-intensive parallel computing in scientific and engineering applications.The Engineering and Scientific Computation Accelerator (ESCA) consists of a control unit and a single instruction multiple data (SIMD) processing element (PE) array,in which PEs communicate with each other via a hierarchical two-level network-on-chip (NoC) with high bandwidth and low latency.We exploit the architecture features of ESCA to implement a parallel FFT algorithm efficiently.Experimental results show that both the proposed parallel FFT algorithm and the ESCA architecture are scalable.The 16-bit fixed-point parallel FFT performance of ESCA is compared with a published work to prove the superiority of the mapping algorithm and the hardware architecture.The floating-point parallel FFT performances of ESCA are evaluated and compared with those of the IBM Cell processor and GPU to demonstrate the computing power of the ESCA system for high performance applications.
文摘The design of reconfigurable multi-butterfly parallel radix-r FFT (Fast Fourier Transform) processors is proposed. FFT is widely used in signal processing, and the application needs real-time and high performance, while most of the traditional designs are limited to the power of two, which wastes the buffers and multipliers in big data. In response to the problem, we improve the parallel FFT algorithm with the design of reconfigurable control machine combined with buffer/multiplier, and the cost function with the input of radix/number/paddling number/time consuming is deduced. Constrained with the number of buffer and multipliers, the radix and number can be computed with the optimum cost function, and the resolution space of computing performance and hardware cost is presented. The proposed guarantees the real-time performance with better flexibility compared with the previous literature, and the comparison also suggests the effectiveness of the design.
文摘为解决并行应用程序使用FFTW(Fastest Fourier Transform in the West)并行软件包所面临的计算规模难以扩展、数据结构变动大、实现不同数据结构间通信难度大、接口不确定等问题,在JASMIN框架内设计实现FFT并行解法器.该解法器封装了数据分布存储、数据通信等并行计算细节,通过重新分布存储数据,调用一维FFT变换实现高维FFT的并行计算,并提供规范接口,支撑用户简便地实现FFT的并行计算.数值测试表明,该解法器具有很好的并行性能.该解法器已应用于激光等离子体成丝不稳定性的数值模拟并行程序,它在2048个处理器上的并行效率可达80%以上.
