模加法器是余数系统(Residue Number System,RNS)的基本运算单元,2n-2k-1形式的余数基易于构建大动态范围和具有优良复杂度平衡性的多通道余数基.基于前缀运算和进位修正算法提出了一类新的模2n-2k-1加法通用算法及其VLSI实现结构.该算...模加法器是余数系统(Residue Number System,RNS)的基本运算单元,2n-2k-1形式的余数基易于构建大动态范围和具有优良复杂度平衡性的多通道余数基.基于前缀运算和进位修正算法提出了一类新的模2n-2k-1加法通用算法及其VLSI实现结构.该算法消除了重复的进位信息计算,且可采用任意已有的前缀运算结构.与同类型模加法器的分析对比结果表明,提出的模2n-2k-1加法器具有优良的"面积×时延"特性.展开更多
This paper presents area efficient architecture of modulo 2<sup>n </sup>- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The p...This paper presents area efficient architecture of modulo 2<sup>n </sup>- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2<sup>n </sup>- 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log<sub>2</sub>n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.展开更多
文摘模加法器是余数系统(Residue Number System,RNS)的基本运算单元,2n-2k-1形式的余数基易于构建大动态范围和具有优良复杂度平衡性的多通道余数基.基于前缀运算和进位修正算法提出了一类新的模2n-2k-1加法通用算法及其VLSI实现结构.该算法消除了重复的进位信息计算,且可采用任意已有的前缀运算结构.与同类型模加法器的分析对比结果表明,提出的模2n-2k-1加法器具有优良的"面积×时延"特性.
文摘This paper presents area efficient architecture of modulo 2<sup>n </sup>- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2<sup>n </sup>- 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log<sub>2</sub>n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.
