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Zero-voltage switching converter absorbing parasitic parameters for super high frequency induction heating 被引量:1
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作者 Zheng-shi WANG Hui-ming CHEN 《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》 SCIE EI CAS CSCD 2008年第4期564-571,共8页
This paper presents a novel mega-Hz-level super high frequency zero-voltage soft-switching converter for induction heating power supplies. The prominent advantage of this topology is that it can absorb both inductive ... This paper presents a novel mega-Hz-level super high frequency zero-voltage soft-switching converter for induction heating power supplies. The prominent advantage of this topology is that it can absorb both inductive and capacitive parasitic components in the converter. The switch devices operate in a zero-voltage soft-switching mode. Consequently, the high voltage and high current spikes caused by parasitic inductors or capacitors oscillation do not occur in this circuit, and the high power loss caused by high frequency switching can be greatly reduced. A large value inductor is adopted between the input capacitor and the switches, thus, this novel converter shares the benefits of both voltage-type and current-type circuits simultaneously, and there are no needs of dead time between two switches. The working principles in different modes are introduced. Results of simulation and experiments operated at around 1 MHz frequency verify the validity of parasitic components absorption and show that this convener is competent for super high frequency applications. 展开更多
关键词 Induction heating Super high frequency Soft-switching converter parasitic parameters
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An Improved Parasitic Parameter Extraction Method for InP HEMT
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作者 DUAN Lanyan LU Hongliang +2 位作者 QI Junjun ZHANG Yuming ZHANG Yimen 《ZTE Communications》 2022年第S01期1-6,共6页
An improved parasitic parameter extraction method for InP high electron mobil-ity transistor(HEMT)is presented.Parasitic parameter extraction is the first step of model parameter extraction and its accuracy has a grea... An improved parasitic parameter extraction method for InP high electron mobil-ity transistor(HEMT)is presented.Parasitic parameter extraction is the first step of model parameter extraction and its accuracy has a great impact on the subsequent internal pa-rameter extraction.It is necessary to accurately determine and effectively eliminate the parasitic effect,so as to avoid the error propagation to the internal circuit parameters.In this paper,in order to obtain higher accuracy of parasitic parameters,parasitic parameters are extracted based on traditional analytical method and optimization algorithm to obtain the best parasitic parameters.The validity of the proposed parasitic parameter extraction method is verified with excellent agreement between the measured and modeled S-param-eters up to 40 GHz for InP HEMT.In 0.1-40 GHz InP HEMT,the average relative error of the optimization algorithm is about 9%higher than that of the analysis method,which verifies the validity of the parasitic parameter extraction method.The extraction of parasit-ic parameters not only provides a foundation for the high-precision extraction of small sig-nal intrinsic parameters of HEMT devices,but also lays a foundation for the high-preci-sion extraction of equivalent circuit model parameters of large signal and noise signals of HEMT devices. 展开更多
关键词 parasitic parameters open-short test structure parameter extraction HEMT
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Influence of Parasitic Parameters on Dynamic Threshold Voltage Hysteresis of Silicon Carbide MOSFETs 被引量:1
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作者 Yumeng Cai Tong Sun +5 位作者 Peng Sun Zhibin Zhao Xuebao Li Hui Wang Zhong Chen Boyuan Cao 《CSEE Journal of Power and Energy Systems》 SCIE EI CSCD 2023年第6期2251-2262,共12页
Threshold voltage (V_(TH)) hysteresis affects the dynamic characteristics of silicon carbide (SiC) MOSFETs, whichin turn affects reliability of a device. In this paper, a dynamichysteresis curve is proposed as an eval... Threshold voltage (V_(TH)) hysteresis affects the dynamic characteristics of silicon carbide (SiC) MOSFETs, whichin turn affects reliability of a device. In this paper, a dynamichysteresis curve is proposed as an evaluation method of theinfluence of V_(TH) hysteresis on the switching characteristics ofSiC MOSFETs. This method can eliminate the impact of triggerlevel and obtain the dynamic V_(TH). Furthermore, the influence ofparasitic parameters on dynamic V_(TH) hysteresis is theoreticallyanalyzed. Double pulse tests under different parasitic parametersare performed on three SiC MOSFETs with different gatestructures to verify the analysis. Results show that gate resistance(R_(G)) and source inductance (L_(S)) have more significant effectson dynamic V_(TH) hysteresis compared with gate inductance anddrain inductance. V_(TH) hysteresis phenomenon weakens withincrease of R_(G) or L_(S), which is related to device structure.The results presented in this paper can provide guidance forthe design of circuit parasitic parameters of SiC MOSFETs toregulate V_(TH) hysteresis. 展开更多
关键词 Dynamic hysteresis curve parasitic parameters silicon carbide(SiC)MOSFETs switching characteristics threshold voltage hysteresis
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Integrated power electronics module based on chip scale packaged power devices 被引量:2
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作者 王建冈 阮新波 《Journal of Southeast University(English Edition)》 EI CAS 2009年第3期367-371,共5页
High performance can be obtained for the integrated power electronics module(IPEM) by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM (HB-... High performance can be obtained for the integrated power electronics module(IPEM) by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM (HB-IPEM), consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management. 展开更多
关键词 integrated power electronics module chip scale package RELIABILITY parasitic parameter thermal management
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Prediction of the conducted EMI in PWM converter system with parasitic parameters considered 被引量:6
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作者 LIANG Bin WEI KeXin YUE YouJun 《Science China(Technological Sciences)》 SCIE EI CAS 2012年第10期2829-2836,共8页
This paper presents a new approach for modeling of the conducted electromagnetic interference(EMI) prediction for widely used converter systems.Coupling paths and mechanism of differential mode(DM) interference and co... This paper presents a new approach for modeling of the conducted electromagnetic interference(EMI) prediction for widely used converter systems.Coupling paths and mechanism of differential mode(DM) interference and common mode(CM) interference have been analyzed.Models to predict the high-frequency noise of PWM converter system are created.A direct calculation method in frequency domain is proposed for the deduction of frequency spectrum.A method is given for obtaining the parasitic parameters and topological structure of the model.An experimental investigation of the conducted emission from an actual high-power rectifier system is described.The validity of the models is confirmed by comparison to laboratory measurements. 展开更多
关键词 parasitic parameter conducted EMI common mode(CM) differential mode(DM)
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The Method of the SiC MOSFET Replacing the Si IGBT in the Traditional Power Electronics Converter without Redesigning the Main Circuit and the Driver Circuit
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作者 Lei Zhang Dejian Yang +3 位作者 Lei Ren Yun Cheng Qiufeng Yan Yinlong Yuan 《Energy Engineering》 EI 2021年第4期1155-1170,共16页
As a wide bandgap power electronics device,the SiC MOSFET has a lot of advantages over the traditional Si IGBT.Replacing the Si IGBT with the SiC MOSFET in the existing power electronics converter is an effective mean... As a wide bandgap power electronics device,the SiC MOSFET has a lot of advantages over the traditional Si IGBT.Replacing the Si IGBT with the SiC MOSFET in the existing power electronics converter is an effective means to improve the performance and promote the upgrading of the traditional converter.Generally,in order to make full use of its advantages of the SiC MOSFET,the Si IGBT in the traditional power electronics circuit cannot be simply replaced by the SiC MOSFET,but the main circuit and the driver circuit need to be redesigned because the oscillation problem and the cross-talk problem caused by the parasitic parameter are very serious when the SiC MOSFET switches.However,considering the low cost and the short cycle requirement of the equipment development,it is often difficult to redesign the circuit hardware structure of all converters.In order to resolve this contradiction,a ferrite bead based method is proposed in this paper.Through this method,without redesigning the hardware structure of the main circuit and the driver circuit,the SiC MOSFET can be used to replace the Si-based power electronics device directly,and the loss of the converter can be reduced with small oscillation.Finally,the effectiveness of the proposed method is proved by experiments. 展开更多
关键词 SiC MOSFET oscillation CROSS-TALK parasitic parameter ferrite bead
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Modeling of High-frequency Electromagnetic Oscillation for DC Fault in MMC-HVDC Systems
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作者 Hong Shen Zhonghao Dongye +4 位作者 Lei Qi Muxue Wang Xiangyu Zhang Peng Qiu Xiaoguang Wei 《CSEE Journal of Power and Energy Systems》 SCIE EI CSCD 2023年第3期1151-1160,共10页
DC short-circuit faults pose a hazard to the operation of a modular multilevel converter(MMC)-based high voltage direct current(HVDC)system,necessitating reliable fault clearing solutions with rapid reaction.However,b... DC short-circuit faults pose a hazard to the operation of a modular multilevel converter(MMC)-based high voltage direct current(HVDC)system,necessitating reliable fault clearing solutions with rapid reaction.However,because the parasitic capacitances of the main equipment oscillate with the lumped inductances of the HVDC system,strong electromagnetic oscillations with multiple frequencies occur during clearance transients.These oscillations will disturb the HVDC system’s protection and control systems.Therefore,this paper focuses on the modeling of these oscillations.First,an equivalent circuit for the MMC-based HVDC system is proposed,taking into account the parasitic capacitances of the system’s major components,such as DC reactors,connecting cables,and DC circuit breakers(DCCBs).Second,four distinct oscillation stages are postulated based on action coordination of MMCs and DCCBs,and the associated analytical equations for the oscillation frequencies are derived.Third,a 200 kV MMC-based DC converter station is subjected to an 6ms/6kA pole-to-pole(PTP)short-circuit test.Electromagnetic oscillations have a frequency range of several kHz to several hundreds of kHz.The measured waveforms correspond well with simulated results,including the parasitic characteristics.Additionally,the relative errors between the simulated and measured frequencies are less than 5%. 展开更多
关键词 DC short-circuit fault electromagnetic oscillation MMC-HVDC parasitic parameter wide-band model
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New Multipole Method for 3-D Capacitance Extraction
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作者 Zhao-ZhiYang Ze-YiWang 《Journal of Computer Science & Technology》 SCIE EI CSCD 2004年第4期544-549,共6页
This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered in... This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap. 展开更多
关键词 3-D interconnect parasitic capacitance extraction IBEM (indirect boundary element method) electronic design automation parasitic parameter extraction VLSI simulation verification
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