New insight into the parasitic bipolar amplification effect in single event transient production

In this paper, a new method is proposed to study the mechanism of charge collection in single event transient （SET） production in 90 nm bulk complementary metal oxide semiconductor （CMOS） technology. We find that different from the case in the pMOSFET, the parasitic bipolar amplification effect （bipolar effect） in the balanced inverter does not exist in the nMOSFET after the ion striking. The influence of the suhstrate process on the bipolar effect is also studied in the pMOSFET. We find that the bipolar effect can be effectively mitigated by a buried deep P＋-well layer and can be removed by a buried SO2 layer.

Temperature dependence of the P-hit single event transient pulse width in a three-transistor inverter chain

A comparison of the temperature dependence of the P-hit single event transient （SET） in a two-transistor （2T） inverter with that in a three-transistor （3T） inverter is carried out based on a three-dimensional numerical simulation. Due to the significantly distinct mechanisms of the single event change collection in the 2T and the 3T inverters, the temperature plays different roles in the SET production and propagation. The SET pulse will be significantly broadened in the 2T inverter chain while will be compressed in the 3T inverter chain as temperature increases. The investigation provides a new insight into the SET mitigation under the extreme environment, where both the high temperature and the single event effects should be considered. The 3T inverter layout structure （or similar layout structures） will be a better solution for spaceborne integrated circuit design for extreme environments.

Theoretical Analysis of Solidly Mounted Film Bulk Acoustic Resonator with Nanocrystalline Diamond as High Impedance Material of Bragg Reflector

In this paper,a solidly mounted resonator(SMR)was designed with nanocrystalline diamond(NCD)as the high acoustic impedance material of Bragg reflector to improve the quality.We used Mathcad to investigate the effect of the Bragg reflector on the performance of the SMR,as well as the influence of different materials and the number of layers of Bragg reflector on the quality factor Q.Results show that the Bragg reflector could reduce energy loss effectively,and the higher the impedance of the high acoustic impedance layer,the better the SMR.The parasitic factors of the SMR using two high acoustic impedance materials,tungsten(W)and NCD,were also simulated by an Advanced Design System(ADS)using the Mason model.It was found that the parasitic effect caused by metal would significantly decrease the Q factor of the SMR.In the frequency range below 6 GHz,within which the SMR works normally,NCD performed better than W.Therefore,NCD is a better choice of high acoustic impedance material in the design of the SMR,with improved quality at high frequency and low loss.The optimum number of layers of Bragg reflector is 6.

A gate driver for parallel connected MOSFETs with crosstalk suppression

New semiconductor materials offer several advantages for modern power systems,including low switching and conduction losses,excellent thermal conduction of a die,and high operation temperature.Avionics is one of the main beneficiaries of the progress in power devices,as it enables more compact and lighter converters for future More Electrical Aircraft.However,these advancements also come with new challenges that must be addressed to avoid potentially dangerous situations and fully utilize the capabilities of fast SiC MOSFETs.One such challenge is the high drain voltage rate during the switching process,which leads to a significant injection of current into the gate circuit(crosstalk effect).This increased current injection increases the risk of shoot-through conduction and thermal runaway.Although preventive measures are well-known,they offer limited protection in the case of parallel MOSFET connections.Therefore,this paper considers crosstalk features for parallel MOSFET connections,such as parasitic inductance of gate driver trace and gate voltage distribution.A special model is proposed to predict the magnitude of induced gate voltage under different conditions considering the nonlinear behavior of the MOSFET reverse capacitance.A new clamp circuit with an individual low-inductance path for each parallel switch is also proposed to suppress the consequences of crosstalk.The modified circuit operates independently from the main gate driver circuit;therefore,it does not change the switching time and electromagnetic interference pattern of the inverter.The efficiency of the new gate driver is confirmed through simulation and experimental results.

Eliminating the floating-body effects in a novel CMOS-compatible thin-SOI LDMOS

A novel CMOS-compatible thin film SOI LDMOS with a novel body contact structure is proposed. It has a Si window and a P-body extended to the substrate through the Si window, thus, the P-body touches the P＋ region to form the body contact. Compared with the conventional floating body SOI LDMOS （FB SOI LDMOS） structure, the new structure increases the off-state BV by 54%, decreases the specific on resistance by 20%, improves the output characteristics significantly, and suppresses the self-heating effect. Furthermore, the advantages of the low leakage current and low output capacitance of SOI devices do not degrade.

A current-mode DAC unit circuit with smooth transition

The digital-to-analogue converter （DAC） plays a significant role in modern electronic systems, and current-mode DACs are widely used due to their excellent properties. However, the non-ideal transition at switching instants of the unit circuit will directly affect the performance of the current-mode DAC. The parasitic effects resulting in non-ideal transition are analyzed in this paper. A simple structure unit circuit is proposed to diminish the non-ideal transition. The simulation results show that the parasitic effects are suppressed effectively, and a smoother output transition is achieved. The feasibility of the proposed current-mode DAC unit circuit is verified by the application in a frequency jitter circuit.

Single event transient pulse attenuation effect in three-transistor inverter chain

In this paper, compared with two-transistor (2T) inverter chain, the production and propagation of P-hit single event transient (SET) in three-transistor (3T) inverter chain is studied in depth based on three-dimensional numerical simulations in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. The pulse attenuation effect is found in 3T inverter chain, and the pulse can not completely propagate through the inverter chain as LET increases. The discovery will provide a new insight into SET hardened design, the 3T inverter layout structure (or similar layout structures) will be a better method in integrated circuits (ICs) design in radiation environment.

Improvements on high voltage performance of power static induction transistors

A novel structure for designing and fabricating a power static induction transistor（SIT）with excellent high breakdown voltage performance is presented.The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance,and to avoid the parallel-current effect in particular.Three ring-shape junctions（RSJ）are arranged around the gate junction to reduce the electric field intensity.It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application.A number of technological methods to increase BVGD and BVGS are presented.The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V,and the performance of the power SIT has been greatly improved.The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.

Reliability testing of a 3D encapsulated VHF MEMS resonator

The frequency stability of a three-dimensional（3D） vacuum encapsulated very high frequency（VHF）disk resonator is systematically investigated. For eliminating the parasitic effect caused by the parasitic capacitance of the printed circuit board（PCB）, a negating capacitive compensation method was developed. The testing results implemented at 25 ℃ for 240 h for the long-term stability indicates that the resonant frequency variation remained within ±1 ppm and the noise floor derived from Allan Deviation was 26 ppb, which is competitive with the conventional quartz resonators. The resonant frequency fluctuation of 1.5 ppm was obtained during 200 temperature cycling between -40 and 85 ℃.