Influence of Parasitic Parameters on Dynamic Threshold Voltage Hysteresis of Silicon Carbide MOSFETs

Threshold voltage (V_(TH)) hysteresis affects the dynamic characteristics of silicon carbide (SiC) MOSFETs, whichin turn affects reliability of a device. In this paper, a dynamichysteresis curve is proposed as an evaluation method of theinfluence of V_(TH) hysteresis on the switching characteristics ofSiC MOSFETs. This method can eliminate the impact of triggerlevel and obtain the dynamic V_(TH). Furthermore, the influence ofparasitic parameters on dynamic V_(TH) hysteresis is theoreticallyanalyzed. Double pulse tests under different parasitic parametersare performed on three SiC MOSFETs with different gatestructures to verify the analysis. Results show that gate resistance(R_(G)) and source inductance (L_(S)) have more significant effectson dynamic V_(TH) hysteresis compared with gate inductance anddrain inductance. V_(TH) hysteresis phenomenon weakens withincrease of R_(G) or L_(S), which is related to device structure.The results presented in this paper can provide guidance forthe design of circuit parasitic parameters of SiC MOSFETs toregulate V_(TH) hysteresis.

An Improved Parasitic Parameter Extraction Method for InP HEMT

An improved parasitic parameter extraction method for InP high electron mobil-ity transistor(HEMT)is presented.Parasitic parameter extraction is the first step of model parameter extraction and its accuracy has a great impact on the subsequent internal pa-rameter extraction.It is necessary to accurately determine and effectively eliminate the parasitic effect,so as to avoid the error propagation to the internal circuit parameters.In this paper,in order to obtain higher accuracy of parasitic parameters,parasitic parameters are extracted based on traditional analytical method and optimization algorithm to obtain the best parasitic parameters.The validity of the proposed parasitic parameter extraction method is verified with excellent agreement between the measured and modeled S-param-eters up to 40 GHz for InP HEMT.In 0.1-40 GHz InP HEMT,the average relative error of the optimization algorithm is about 9%higher than that of the analysis method,which verifies the validity of the parasitic parameter extraction method.The extraction of parasit-ic parameters not only provides a foundation for the high-precision extraction of small sig-nal intrinsic parameters of HEMT devices,but also lays a foundation for the high-preci-sion extraction of equivalent circuit model parameters of large signal and noise signals of HEMT devices.

The Method of the SiC MOSFET Replacing the Si IGBT in the Traditional Power Electronics Converter without Redesigning the Main Circuit and the Driver Circuit

As a wide bandgap power electronics device,the SiC MOSFET has a lot of advantages over the traditional Si IGBT.Replacing the Si IGBT with the SiC MOSFET in the existing power electronics converter is an effective means to improve the performance and promote the upgrading of the traditional converter.Generally,in order to make full use of its advantages of the SiC MOSFET,the Si IGBT in the traditional power electronics circuit cannot be simply replaced by the SiC MOSFET,but the main circuit and the driver circuit need to be redesigned because the oscillation problem and the cross-talk problem caused by the parasitic parameter are very serious when the SiC MOSFET switches.However,considering the low cost and the short cycle requirement of the equipment development,it is often difficult to redesign the circuit hardware structure of all converters.In order to resolve this contradiction,a ferrite bead based method is proposed in this paper.Through this method,without redesigning the hardware structure of the main circuit and the driver circuit,the SiC MOSFET can be used to replace the Si-based power electronics device directly,and the loss of the converter can be reduced with small oscillation.Finally,the effectiveness of the proposed method is proved by experiments.

Modeling of High-frequency Electromagnetic Oscillation for DC Fault in MMC-HVDC Systems

DC short-circuit faults pose a hazard to the operation of a modular multilevel converter(MMC)-based high voltage direct current(HVDC)system,necessitating reliable fault clearing solutions with rapid reaction.However,because the parasitic capacitances of the main equipment oscillate with the lumped inductances of the HVDC system,strong electromagnetic oscillations with multiple frequencies occur during clearance transients.These oscillations will disturb the HVDC system’s protection and control systems.Therefore,this paper focuses on the modeling of these oscillations.First,an equivalent circuit for the MMC-based HVDC system is proposed,taking into account the parasitic capacitances of the system’s major components,such as DC reactors,connecting cables,and DC circuit breakers(DCCBs).Second,four distinct oscillation stages are postulated based on action coordination of MMCs and DCCBs,and the associated analytical equations for the oscillation frequencies are derived.Third,a 200 kV MMC-based DC converter station is subjected to an 6ms/6kA pole-to-pole(PTP)short-circuit test.Electromagnetic oscillations have a frequency range of several kHz to several hundreds of kHz.The measured waveforms correspond well with simulated results,including the parasitic characteristics.Additionally,the relative errors between the simulated and measured frequencies are less than 5%.

New Multipole Method for 3-D Capacitance Extraction

This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap.