Data Gathering in Wireless Sensor Networks Via Regular Low Density Parity Check Matrix

A great challenge faced by wireless sensor networks(WSNs) is to reduce energy consumption of sensor nodes. Fortunately, the data gathering via random sensing can save energy of sensor nodes. Nevertheless, its randomness and density usually result in difficult implementations, high computation complexity and large storage spaces in practical settings. So the deterministic sparse sensing matrices are desired in some situations. However,it is difficult to guarantee the performance of deterministic sensing matrix by the acknowledged metrics. In this paper, we construct a class of deterministic sparse sensing matrices with statistical versions of restricted isometry property(St RIP) via regular low density parity check(RLDPC) matrices. The key idea of our construction is to achieve small mutual coherence of the matrices by confining the column weights of RLDPC matrices such that St RIP is satisfied. Besides, we prove that the constructed sensing matrices have the same scale of measurement numbers as the dense measurements. We also propose a data gathering method based on RLDPC matrix. Experimental results verify that the constructed sensing matrices have better reconstruction performance, compared to the Gaussian, Bernoulli, and CSLDPC matrices. And we also verify that the data gathering via RLDPC matrix can reduce energy consumption of WSNs.

An efficient RNS parity checker for moduli set{2~n-1,2~n+1,2^(2n)+1}and its applications

Residue number system （RNS） has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, sub- traction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory （CRT） and mixed radix conversion （MRC） for the moduli set {2^n-1, 2^n＋1, 2^2n＋1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS.

Low-Density Parity-Check Codes: Research Status and Development Direction

In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the analysis of the code rate and parameters of these eight kinds of structures, we find that the construction of low-density parity-check matrix tends to be more flexible and the parameter variability is enhanced. We propose that the current development cost should be lower with the progress of electronic technology and we need research on more practical Low-Density Parity-Check Codes (LDPC). Combined with the application of the quantum distribution key, we urgently need to explore the research direction of relevant theories and technologies of LDPC codes in other fields of quantum information in the future.

A Fast Filling Algorithm for Image Restoration Based on Contour Parity

Filling techniques are often used in the restoration of images.Yet the existing filling technique approaches either have high computational costs or present problems such as filling holes redundantly.This paper proposes a novel algorithm for filling holes and regions of the images.The proposed algorithm combines the advantages of both the parity-check filling approach and the region-growing inpainting technique.Pairing points of the region’s boundary are used to search and to fill the region.The scanning range of the filling method is within the target regions.The proposed method does not require additional working memory or assistant colors,and it can correctly fill any complex contours.Experimental results show that,compared to other approaches,the proposed algorithm fills regions faster and with lower computational cost.

Construction of protograph LDPC codes with circular generator matrices

The application of protograph low density parity check （LDPC） codes involves the encoding complexity problem. Since the generator matrices are dense, and if the positions of ＂1＂ s are irregularity, the encoder needs to store every ＂1＂ of the generator matrices by using huge chip area. In order to solve this problem, we need to design the protograph LDPC codes with circular generator matrices. A theorem concerning the circulating property of generator matrices of nonsingular protograph LDPC codes is proposed. The circulating property of generator matrix of nonsingular protograph LDPC codes can be obtained from the corresponding quasi-cyclic parity check matrix. This paper gives a scheme of constructing protograph LDPC codes with circulating generator matrices, and it reveals that the fast encoding algorithm of protograph LDPC codes has lower encoding complexity under the condition of the proposed theorem. Simulation results in ad- ditive white Gaussian noise （AWGN） channels show that the bit error rate （BER） performance of the designed codes based on the proposed theorem is much better than that of GB20600 LDPC codes and Tanner LDPC codes.

Construction of time-frequency codes based on protograph LDPC codes in OFDM communication systems

This paper proposes a scheme to construct time- frequency codes based on protograph low density parity check （LDPC） codes in orthogonal frequency division multiplexing （OFDM） communication systems. This approach synthesizes two techniques： protograph LDPC codes and OFDM. One symbol of encoded information by protograph LDPC codes corresponds to one sub-carrier, namely the length of encoded information equals to the number of sub-carriers. The design of good protograph LDPC codes with short lengths is given, and the proposed proto- graph LDPC codes can be of fast encoding, which can reduce the encoding complexity and simplify encoder hardware implementa- tion. The proposed approach provides a higher coding gain in the Rayleigh fading channel. The simulation results in the Rayleigh fading channel show that the bit error rate （BER） performance of the proposed time-frequency codes is as good as random LDPC- OFDM codes and is better than Tanner LDPC-OFDM codes under the condition of different fading coefficients.

High Robust Broadcasting over DTMB-A with Low-rate LDPC Codes

As the 2nd generation digital terrestrial television broadcasting(DTTB)standard,digital terrestrial/television multimedia broadcasting-advanced(DTMB-A)can provide higher spectrum efficiency and transmission reliability by adopting flexible frame structure and advanced forward error correction coding compared with the 1 st generation DTTB systems.In order to increase the flexibility and robustness of the DTTB network,the frequency reuse scheme of factor one(reuse-1)is proposed,where the same RF channel is used by different stations covering the adjacent service areas.However,it demands a very low carrier-tonoise ratio(C/N)threshold below 0 dB at the DTTB physical layer.In this paper,a robust broadcasting technique is proposed based on DTMB-A with newly designed low-rate low density parity check(LDPC)codes.By adopting quasi-cyclic(QC)Raptor-like structure and progressive lifting method,the high performance low-rate LDPC codes are designed supporting multiple code lengths.Both density-evolution analyses and laboratory measurements demonstrate that DTMB-A with low-rate coding can complete the demodulation reliably with the C/N threshold below0 d B,which is one important necessary condition to support frequency reuse-1 scheme.

Performance analysis of LDPC codes on OOK terahertz wireless channels

Atmospheric absorption, scattering, and scintillation are the major causes to deteriorate the transmission quality of terahertz（THz） wireless communications. An error control coding scheme based on low density parity check（LDPC） codes with soft decision decoding algorithm is proposed to improve the bit-error-rate（BER） performance of an on-off keying（OOK） modulated THz signal through atmospheric channel. The THz wave propagation characteristics and channel model in atmosphere is set up. Numerical simulations validate the great performance of LDPC codes against the atmospheric fading and demonstrate the huge potential in future ultra-high speed beyond Gbps THz communications.

Quaternion Integers Based Higher Length Cyclic Codes and Their Decoding Algorithm

The decoding algorithm for the correction of errors of arbitrary Mannheim weight has discussed for Lattice constellations and codes from quadratic number fields.Following these lines,the decoding algorithms for the correction of errors of n=p−12 length cyclic codes(C)over quaternion integers of Quaternion Mannheim(QM)weight one up to two coordinates have considered.In continuation,the case of cyclic codes of lengths n=p−12 and 2n−1=p−2 has studied to improve the error correction efficiency.In this study,we present the decoding of cyclic codes of length n=ϕ(p)=p−1 and length 2n−1=2ϕ(p)−1=2p−3(where p is prime integer andϕis Euler phi function)over Hamilton Quaternion integers of Quaternion Mannheim weight for the correction of errors.Furthermore,the error correction capability and code rate tradeoff of these codes are also discussed.Thus,an increase in the length of the cyclic code is achieved along with its better code rate and an adequate error correction capability.

Optimized LDPC differential-encoded 16QAM scheme for high-speed transmission systems

The 16-ary quadrature amplitude modulation （16QAM） is a high spectral efficient scheme for high-speed transmission systems. To remove the phase ambiguity in the coherent detection system, differential-encoded 16QAM （DE-16QAM） is usually used, however, it will cause performance degradation about 3 dB as compared to the conventional 16QAM. To overcome the performance loss, a serial concatenated system with outer low density parity check （LDPC） codes and inner DE-16QAM is proposed. At the receiver, joint iterative differential demodulation and decoding （ID） is carried out to approach the maximum likelihood performance. Moreover, a genetic evolution algorithm based on the extrinsic information transfer chart is proposed to optimize the degree distribution of the outer LDPC codes. Both theoretical analyses and simulation results indicate that this algorithm not only compensates the performance loss, but also obtains a significant performance gain, which is up to 1 dB as compared to the conventional non-DE-16QAM.

Area-efficient analog decoder design for low density parity check codes in deep-space applications

Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verily the approach is tully integrated in a four-metal double-poly 0.35 lam complementary metal oxide semiconductor （CMOS） technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable lbr space- and power-constrained spacecraft system.

An Enhanced LDPC Coded Partial Incremental Redundancy HARQ Scheme

An enhanced scheme is proposed for high code rate low density parity check （LDPC） coded partial incremental redundancy （PIR） hybrid automatic repeat request （HARQ）. It employs the unequal error protection （UEP） technique for incremental redundancy bits and uses the constellation rearrangement （CoRe） technique for information bits in retransmissions so as to reduce the reliability variances of all encoded bits after soft combining. Simulation results show that the proposed scheme applies to both regular LDPC and irregular LDPC cases and can efficiently improve frame error rate （FER） performance and throughput performance.

A NOVEL CONSTRUCTION OF QUANTUM LDPC CODES BASED ON CYCLIC CLASSES OF LINES IN EUCLIDEAN GEOMETRIES

The dual-containing (or self-orthogonal) formalism of Calderbank-Shor-Steane (CSS) codes provides a universal connection between a classical linear code and a Quantum Error-Correcting Code (QECC). We propose a novel class of quantum Low Density Parity Check (LDPC) codes constructed from cyclic classes of lines in Euclidean Geometry (EG). The corresponding constructed parity check matrix has quasi-cyclic structure that can be encoded flexibility, and satisfies the requirement of dual-containing quantum code. Taking the advantage of quasi-cyclic structure, we use a structured approach to construct Generalized Parity Check Matrix (GPCM). This new class of quantum codes has higher code rate, more sparse check matrix, and exactly one four-cycle in each pair of two rows. Ex-perimental results show that the proposed quantum codes, such as EG(2,q)II-QECC, EG(3,q)II-QECC, have better performance than that of other methods based on EG, over the depolarizing channel and decoded with iterative decoding based on the sum-product decoding algorithm.

LDPC Code’s Decoding Algorithms for Wireless Sensor Network:a Brief Review

As an effective error correction technology,the Low Density Parity Check Code(LDPC)has been researched and applied by many scholars.Meanwhile,LDPC codes have some prominent performances,which involves close to the Shannon limit,achieving a higher bit rate and a fast decoding.However,whether these excellent characteristics are suitable for the resource-constrained Wireless Sensor Network(WSN),it seems to be seldom concerned.In this article,we review the LDPC code’s structure brief.ly,and them classify and summarize the LDPC codes’construction and decoding algorithms,finally,analyze the applications of LDPC code for WSN.We believe that our contributions will be able to facilitate the application of LDPC code in WSN.

Direct measurement of the concurrence for two-qubit electron spin entangled pure state based on charge detection

We propose a protocol for directly measuring the concurrence of a two-qubit electronic pure entangled state. To complete this task, we first design a parity-check measurement（PCM） which is constructed by two polarization beam splitters（PBSs） and a charge detector. By using the PCM for three rounds, we can achieve the concurrence by calculating the total probability of picking up the odd parity states from the initial states. Since the conduction electron may be a good candidate for the realization of quantum computation, this protocol may be useful in future solid quantum computation.

Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.

Multiple accumulated-crossover parallel concatenated SPC codes

By constructing an accumulated-crossover relationship in multiple parallel concatenated single parity check （M-PC-SPC） codes, a class of error-correcting codes, termed multiple accumulated-crossover parallel concatenated single parity check （M-ACPC-SPC） codes, is proposed. M-ACPC-SPC codes possess linear encoding complexity and can be decoded iteratively with low complexity by the sum-product algorithm （SPA）. Simulation results show that M-ACPC-SPC codes have lower error floors than M-PCSPC codes with the same dimension, and when the dimension is 5, M-ACPC-SPC codes achieve bit error rate （BER） better than （3, 6） regular low density parity check （LDPC） codes.

LDPC Decoder for CCSDS Code by Flipping Bits and Fetching Words

The well-known CCSDS(consultative committee for space data systems) LDPC(low density parity check) code for near-earth applications is discussed and used for a case study of Mc Eliece system. First, a data error is picked out with the CCSDS LDPC code. The problem with its generator matrix is illustrated and overcome by a shortened code with some middle code bits deleted. In correspondence, its parity check matrix is also revised with the new quasi-cyclic(QC)-LDPC code. Second, a fast decoding scheme for general QC-LDPC codes is proposed based on flipping bits and fetching words. Besides, a lightweight CCSDS LDPC code based Mc Eliece system can be set up with such codes. The repaired CCSDS LDPC code is supposed to be still useful for communications and storages, and the normalized decoding algorithm is also efficient for general QC-LDPC codes.

Low Complexity LDPC Decoder with Modified Sum-Product Algorithm

This paper describes an efficient implementation of the Sum-Product Algorithm （SPA） within a Low Density Parity Check （LDPC） code decoder, where a horizontal process correction term is used to improve the decocling performance of the Min-Sum algorithms. The correction term is implemented as a look-up table. The algorithm uses the correction term redundancy by means of a coordinate transformation to reduce the hardware complexity. Simulations and hardware tests indicate that the decoding performance is very good with the appropriate look-up table

Improved distinguisher for Achterbahn-128 stream cipher

Achterbahn-128 is a stream cipher proposed by Gammel et al. and submitted to the eSTREAM project. Though many attacks have been published, no recovery attack better than Naya-Plasencia＇ s results with 256 bit keystream limitation. Similar approach is shown and found a specific parity check and decimation. Then an improved distinguisher is constructed for Achterbahn-128 to recover the key with only O （255） keystream bit and O （2102） time complexity. Furthermore, this result is much more effective than the former.