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Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits
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作者 魏道政 《Journal of Computer Science & Technology》 SCIE EI CSCD 1990年第2期156-163,共8页
Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostco... Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone. 展开更多
关键词 A Fault Simulation Algorithm for Combinational Circuits Parallel Critical path tracing path SIMULATION
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THE GLOBALIZATION OF DURAND-KERNER ALGORITHM
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作者 赵风光 王德人 《Applied Mathematics and Mechanics(English Edition)》 SCIE EI 1997年第11期0-0,0-0+0-0+0-0+0-0+0-0+0,共13页
Making use of the theory of continuous homotopy and the relation betweensymmetric polynomtal and polynomtal in one variable the arthors devoted ims article to constructing a regularly homotopic curve with probability ... Making use of the theory of continuous homotopy and the relation betweensymmetric polynomtal and polynomtal in one variable the arthors devoted ims article to constructing a regularly homotopic curve with probability one. Discrete tracingalong this honlotopic curve leads 10 a class of Durand-Kerner algorithm with stepparameters. The convergernce of this class of algorithms is given, which solves theconjecture about the global property of Durand-Kerner algorithm. The.problem forsteplength selection is thoroughly discussed Finally, sufficient numerical examples areused to verify our theory 展开更多
关键词 Durand-Kerner algorithm continuous homotopy path tracing global convergence point estimation
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Accelerated Techniques in Stem Fault Simulation
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作者 石茵 魏道政 《Journal of Computer Science & Technology》 SCIE EI CSCD 1996年第6期551-561,共11页
In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in p... In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously. 展开更多
关键词 Fault simulation critical path tracing parallel pattern evaluation stem fault simulation explicit fault simulation
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