Pattern dependence in synergistic effects of total dose on single-event upset hardness

The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.

The ICM method with objective function transformed by variable discrete condition for continuum structure

ICM （Independent Continuous Mapping） method can solve topological optimization problems with the minimized weight as the objective and subjected to displacement constraints. To get a clearer topological configuration, by introducing the discrete condition of topological variables and integrating with the original objective, an optimal model with multi-objectives is formulated to make the topological variables approach 0 or 1 as near as possible, and the model reduces the effect of deleting rate on the result. The image-filtering method is employed to eliminate the checkerboard patterns and mesh dependence that occurred in the topology optimization of a continuum structure. The computational efficiency is enhanced through selecting quasi-active displacement constraints and a design region. Numerical examples indicate that this algorithm is robust and practicable, though the number of iterations is slightly increased with respect to the original algorithm.

Effects of pattern characteristics on the copper electroplating process

The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width, line spacing and metal density. A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process. By checking test data such as field height, array height, step height and SEM photos, some conclusions are made. Line width is a critical factor of topographical shapes such as the step height and height difference. After the electroplating process, the fine line has a thicker copper thickness, while the wide line has the greatest step height. Three typical topographies, conformal-fill, supper-fill and over-fill, are observed. Moreover, quantified effects are found using the test data and explained by theory, which can be used to develop electroplating process modeling and design for manufacturability （DFM） research.