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BEST WEIGHT PATTERN EVALUATION BASED SECURITY CONSTRAINED POWER DISPATCH ALGORITHM
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作者 Lakhwinder SINGH J.S. DHILLON 《Journal of Systems Science and Systems Engineering》 SCIE EI CSCD 2007年第3期287-307,共21页
This paper presents a methodology which determines the allocation of power demand among the committed generating units while minimizes number of objectives as well as meets physical and technological system constraint... This paper presents a methodology which determines the allocation of power demand among the committed generating units while minimizes number of objectives as well as meets physical and technological system constraints. The procedure considers two decoupled problems based upon the dependency of their goals on either active power or reactive power generation. Both the problems have been solved sequentially to achieve optimal allocation of active and reactive power generation while minimizes operating cost, gaseous pollutants emission objectives and active power transmission loss with consideration of system operating constraints along with generators prohibited operating zones and transmission line flow limits. The active and reactive power line flows are obtained with the help of generalized generation shift distribution factors (GGDF) and generalized Z-bus distribution factors (GZBDF), respectively. First problem is solved in multi-objective framework in which the best weights assigned to objectives are determined while employing weighting method and in second problem, active power loss of the system is minimized subject to system constraints. The validity of the proposed method is demonstrated on 30-bus IEEE power system. 展开更多
关键词 Multi-objective optimization best weight pattern evaluation fuzzy decision making membership function generalized generation shift distribution factors generalised Z-bus distribution factors
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Posterior probability calculation procedure for recognition rate comparison 被引量:1
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作者 Jun He Qiang Fu 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2016年第3期700-711,共12页
This paper focuses on the recognition rate comparison for competing recognition algorithms, which is a common problem of many pattern recognition research areas. The paper firstly reviews some traditional recognition ... This paper focuses on the recognition rate comparison for competing recognition algorithms, which is a common problem of many pattern recognition research areas. The paper firstly reviews some traditional recognition rate comparison procedures and discusses their limitations. A new method, the posterior probability calculation(PPC) procedure is then proposed based on Bayesian technique. The paper analyzes the basic principle, process steps and computational complexity of the PPC procedure. In the Bayesian view, the posterior probability represents the credible degree(equal to confidence level) of the comparison results. The posterior probability of correctly selecting or sorting the competing recognition algorithms is derived, and the minimum sample size requirement is also pre-estimated and given out by the form of tables. To further illustrate how to use our method, the PPC procedure is used to prove the rationality of the experiential choice in one application and then to calculate the confidence level with the fixed-size datasets in another application. These applications reveal the superiority of the PPC procedure, and the discussions about the stopping rule further explain the underlying statistical causes. Finally we conclude that the PPC procedure achieves all the expected functions and be superior to the traditional methods. 展开更多
关键词 pattern recognition performance evaluation algorithm uncertainty analysis
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Accelerated Techniques in Stem Fault Simulation
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作者 石茵 魏道政 《Journal of Computer Science & Technology》 SCIE EI CSCD 1996年第6期551-561,共11页
In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in p... In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously. 展开更多
关键词 Fault simulation critical path tracing parallel pattern evaluation stem fault simulation explicit fault simulation
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