Pixel and Column Fixed Pattern Noise Suppression Mechanism in CMOS Image Sensor

A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.

Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

A New CMOS Image Sensor with a High Fill Factor and the Dynamic Digital Double Sampling Technique

A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.

Computer Simulation of Compensation Method for Infrared Focal Plane Array

A major motivation for this work is to investigate a method of computer simulation for compensating fixed pattern noise of the infrared focal plane arrays. A mathematical model of the output signal of focal plane array was established; a compensating algorithm utilizing reference source was derived and simulating programs were designed. The images of compensating process verify the influence of nonuniformity of responsibility and offset on fixed pattern noise. The result show that simulating method of investigating compensation technology for focal plane arrays is feasible, the generated images and methods can be used to the study of image recognition.

320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.

Novel Logarithmic Active Pixel Sensor with High Dynamic Range and High Output Swing

The logarithmic response complementary metal oxide semiconductor （CMOS） image sensor provides a wide dynamic range, but its drawback is the lack of simple fixed pattern noise（FPN） cancellation scheme. Designed is a novel logarithmic active pixel sensor（APS） with high dynamic range and high output swing. Firstly, the operation principle of mixed-model APS is introduced. The pixel can work in three operation modes by choosing the proper control signals. Then, FPN sources of logarithmic APS are analyzed, and double-sampled technique is implemented to reduce FPN. Finally, according to the simulation results, layout is designed and has passed design rule check（DRC）, electronic rule eheck（ERC） and layout versus schematic（LVS） verifications, and the post-simulation results are basically in agreement with the simulation results. Dynamic range of the new logarithmic APS can reach about 140 dB; and the output swing is about 750 inV. Results show that by using double sampled technique, most FPN is eliminated and the dynamic range is enhanced.

DESIGN AND IMPLEMENTATION OF CMOS IMAGE SENSOR

A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

Noise in a CMOS digital pixel sensor

Based on the study of noise performance in CMOS digital pixel sensor （DPS）, a mathematical model of noise is established with the pulse-width-modulation （PWM） principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator＇s reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.