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A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme 被引量:1
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作者 陈昊 刘力源 +2 位作者 李冬梅 张春 王志华 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第10期104-109,共6页
A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6+6 architecture and requires no calibration. ... A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6+6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm^2. 展开更多
关键词 current steering DAC gradient error switching scheme static performance testing method
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