Design and Realization of a Monolithic GaAs 3Bit Phase Digitizing DAC

Design,realization,and test of a monolithic GaAs 3bit phase digitizing DAC for 3bit digital radio-frequency memory are detailedly described.The 0.5μm fully ion-implanted GaAs MESFET is used to fabricate the circuit in Nanjing Electronic Devices Institute’s (NEDI’s) 75mm standard process line.The high-speed DAC is designed with on-wafer 50Ω I/O impedance matching.Test results show that its work bandwidth is more than 1.5GHz,and phase accuracy is better than 4%.Its code conversion rate can be higher than 12Gbps.

Direct Digital Frequency Control Based on the Phase Step Change Characteristic between Signals

We present a new digital phase lock technology to achieve the frequency control and transformation through high precision multi-cycle group synchronization between signals without the frequency transformation circuit. In the case of digital sampling, the passing zero point of the phase of the controlled signal has the phase step characteristic, the phase step of the passing zero point is monotonic continuous with high resolution in the phase lock process, and using the border effect of digital fuzzy area, the gate can synchronize with the two signals, the quantization error is reduced. This technique is quite different from the existing methods of frequency transformation and frequency synthesis, the phase change characteristic between the periodic signals with different nominal is used. The phase change has the periodic phenomenon, and it has the high resolution step value. With the application of the physical law, the noise is reduced because of simplifying frequency transformation circuits, and the phase is locked with high precision. The regular phase change between frequency signals is only used for frequency measurement, and the change has evident randomness, but this randomness is greatly reduced in frequency control, and the certainty of the process result is clear. The experiment shows that the short term frequency stability can reach 10-12/s orders of magnitude.

A convenient look-up-table based method for the compensation of non-linear error in digital fringe projection

Although the structured light system that uses digital fringe projection has been widely implemented in three-dimensional surface profile measurement, the measurement system is susceptible to non-linear error. In this work, we propose a convenient look-up-table-based （LUT-based） method to compensate for the non-linear error in captured fringe patterns. Without extra calibration, this LUT-based method completely utilizes the captured fringe pattern by recording the full-field differences. Then, a phase compensation map is established to revise the measured phase. Experimental results demonstrate that this method works effectively.

Approach to blind estimation of the PN sequence in DS-SS signals with residual carrier

This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.

DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers

This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.

Dynamic balancing with rotating radial electromagnetic force

A method of producing rotating radial electromagnetic force with a separable structure is proposed, and an experimental model was designed on which open loop vibration control experiments were carried out. Experimental results prove that the electromagnetic force designed has a constant magnitude and an uniform speed, and the idea of using an electromagnetic force as an active control in automatic balancing is correct in principle, and practicable in engineering.

Fixed Point Iteration Chaos Controlled ZCDPLL

The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.

FPGA based digital phase-coding quantum key distribution system

Quantum key distribution （QKD） is a technology with the potential capability to achieve information-theoretic security. Phase- coding is an important approach to develop practical QKD systems in fiber channel. In order to improve the phase-coding modulation rate, we proposed a new digital-modulation method in this paper and constructed a compact and robust prototype of QKD system using currently available components in our lab to demonstrate the effectiveness of the method. The system was deployed in laboratory environment over a 50 km fiber and continuously operated during 87 h without manual interaction. The quantum bit error rate （QBER） of the system was stable with an average value of 3.22% and the secure key generation rate is 8.91 kbps. Although the modulation rate of the photon in the derno system was only 200 MHz, which was limited by the Faraday- Michelson interferometer （FMI） structure, the proposed method and the field programmable gate array （FPGA） based electronics scheme have a great potential for high speed QKD systems with Giga-bits/second modulation rate.

Three-Dimensional Shape Measuring Method Based on Dual-Frequency Digital Moiré Fringe

A dual-frequency digital Moiré measurement method(DFDM) is proposed for the three-dimensional(3D) shape measurement of an object.The high-and low-frequency fringes are modulated separately along orthogonal direction using different carrier frequencies before being projected onto the measured object.After collecting and demodulating the composite fringe,the digital π phase shift is used to remove the DC component of the demodulated fringes,resulting in high-precision Moiré fringes for calculating the wrapped phase.The unwrapping of the high-frequency wrapped phase is guided by the low-frequency phase to further realistically reconstruct the surface of the measured object.When compared with existing single-shot digital Moiré profilometry,DFDM effectively removes the DC component of the fringe and calculates the phase more accurately.