Robust CMOS phase frequency detector for high speed and low jitter charge pump PLL

In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.

A super-high resolution frequency standard measuring approach based on phase coincidence characteristics between signals

A method for super high resolution comparison measurement is proposed in this paper with a comparison between the frequency standards of different nominal frequencies, which is based on phase coincidence detection of the two compared signals. It utilizes the regular phase shift characteristics between the signals. The resolution of the measurement approach can reach 10^-13/s at 5 MHz, and the self-calibration resolution can achieve 10^-14/s in the comparison between 10 MHz and 100 MHz, or even can reach 10^-15/s in the comparison between 10 MHz and 190 MHz. This method implies significant progress in the development of the high precision frequency standard comparison technology.

Design of 0.5V low-voltage phase and frequency detector for frequency synthesizer in wireless sensor networks

Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.

Modulation Recognition with Frequency Offset and Phase Offset over Multipath Channels

Modulation recognition becomes unreliable at low signal-to-noise ratio(SNR)over fading channel.A novel method is proposed to recognize the digital modulated signals with frequency and phase offsets over multi-path fading channels in this paper.This method can overcome the effects of phase offset,Gaussian noise and multi-path fading.To achieve this,firstly,the characteristic parameters search is constructed based on the cyclostationarity of received signals,to overcome the phase offset,Gaussian white noise,and influence caused by multi-path fading.Then,the carrier frequency of the received signal is estimated,and the maximum characteristic parameter is searched around the integer multiple carriers and their vicinities.Finally,the modulation types of the received signal with frequency and phase offsets are classified using decision thresholds.Simulation results demonstrate that the performance of the proposed method is better than the traditional methods when SNR is over 5dB,and that the proposed method is robust to frequency and phase offsets over multipath channels.

Phase-related noise characteristics of 780 nm band single-frequency lasers used in the cold atomic clock

We propose a method to directly measure phase-related noise characteristics of single-frequency lasers in the 728–980 nm band based on a 120°phase difference interferometer.Differential phase information of the laser under test is demodulated via the interferometer.Other parameters related to the phase noise characteristics such as linewidth at different observation time, phase/frequency noise, power spectrum density of phase/frequency fluctuation, and Allan deviation are further obtained.Frequency noise as low as 1 Hz^2/Hz can be measured using our system.Then the phase-related noise characteristics of two commercial lasers frequently used in cold atomic clocks are studied systematically by the method.Furthermore, several influencing factors and their relative evolution laws are also revealed, such as the pump current and frequency-locking control parameters.This would help to optimize the laser performance, select laser sources, and evaluate the system performance for cold atomic physics applications.

Direct Digital Frequency Control Based on the Phase Step Change Characteristic between Signals

We present a new digital phase lock technology to achieve the frequency control and transformation through high precision multi-cycle group synchronization between signals without the frequency transformation circuit. In the case of digital sampling, the passing zero point of the phase of the controlled signal has the phase step characteristic, the phase step of the passing zero point is monotonic continuous with high resolution in the phase lock process, and using the border effect of digital fuzzy area, the gate can synchronize with the two signals, the quantization error is reduced. This technique is quite different from the existing methods of frequency transformation and frequency synthesis, the phase change characteristic between the periodic signals with different nominal is used. The phase change has the periodic phenomenon, and it has the high resolution step value. With the application of the physical law, the noise is reduced because of simplifying frequency transformation circuits, and the phase is locked with high precision. The regular phase change between frequency signals is only used for frequency measurement, and the change has evident randomness, but this randomness is greatly reduced in frequency control, and the certainty of the process result is clear. The experiment shows that the short term frequency stability can reach 10-12/s orders of magnitude.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

Effect of Heat-treatment on Crystalline Phase and UV Absorption of 60CeO_2-40TiO_2 Thin Films by Magnetron Sputtering

60CeO2-40TiO2 thin films were deposited on soda-lime silicate glass substrates by R.F. magnetron sputtering. The effects of heat-treatment on the UV-absorption of the thin films were studied on the 60CeO2-40TiO2 thin film with the largest UV cut-off wavelength. The sample films with CeO2：TiO2=60：40 were heated at 773 K, 873 K, 973 K for 30 min. These films are characterized by X-ray diffraction （XRD）, scanning electron microscopy （SEM）, and X-ray photoelectron spectroscopy and spectrometer （XPS）. XRD analysis proves that the addition of TiO2 to CeO2 changed the crystalline state of CeO2. But the UV absorption effect of CeO2-TiO2 films with CeO2 crystallite phase is inferior to that of the amorphous phase CeO2-TiO2 films. XPS analysis also indicates that the amorphous phase CeO2-TiO2 films have the most Ce3＋ content in these films. Amorphous phase and crystalline phase of the CeO2-TiO2 films have different effects on UV absorption of the thin films.

Synchronization for the Environment of OFDM Cooperative Communications Based on Preamble Design and Phase Rotation

Timing and carrier frequency offset estimation are critical issue for OFDM cooperative communications. In view of the complexity and high accuracy requirement, 1/2 and 1/4 pilot symbol cycle CAZAC sequence structures are defined as the pilot frequency sequence. Estimation within one symbol cycle is carried out through averaging samples of two neighboring symbol cycles, after which the operation is expanded to all the symbol cycles in one band group. Taking multipath effect into account, the concept of phase rotation is proposed for a further step. Adjust the phase difference of estimated symbols by phase rotation, and cross estimation could be done. Meanwhile, timing scheme works within one cycle training sequence. Theoretical and simulation analysis indicate that CRLB does not only relate to estimation symbol length, but also be influenced by phase difference of estimation symbols seriously. In the condition that the length of estimation is fixed, the bigger the phase rotation angle is, the smaller the CRLB is. The complexity of proposed algorithm is less than full cycle average estimation method for almost 50%. Meanwhile, the estimation accuracy is approximate with the full cycle average estimation method as well. Timing scheme with the defined preamble structure is also proposed. Simulation proves its efficiency.

A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.

A NOVEL SEMI-BLIND TIME-FREQUENCY DOMAIN TRACKING ALGORITHM SUITABLE FOR MPSK-OFDM

This paper presents a semi-blind tracking algorithm used for Multiple Phase Shift Keying based Orthogonal Frequency Division Multiplexing(MPSK-OFDM) system. By using special pream-bles to assist the decision of a feedback loop and to solve the problem of phase ambiguity,the tracking performance of the algorithm has been improved greatly. Only a few preambles are needed in the al-gorithm since the preambles are not used to estimate the frequency offset but used to provide the variation information of the phase due to the presence of frequency offset. Simulations verify that the algorithm has low SNR bound for tracking as well as high tracking accuracy and the tracking range is expanded to 30% of one subcarrier spacing.

A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

Research on Magnetically Coupled Resonant Detection Method for Breakpoint of Four Mesh Grounding Grid

Magnetically coupled resonant technology is a novel method for solving the breakpoint locating of power grounding grid.But the method can only detect breakpoints of a single mesh grounding grid at present.In this paper,a magnetically coupled resonant detection method for four-hole grounding grid breakpoint is proposed.Firstly,the equivalent circuit model of the four mesh grounding grid with two types of breakpoints,namely edge branch and intermediate branch,is established.The input impedance and phase angle of the system are obtained by analyzing the equivalent capacitance and equivalent resistance in the model.Secondly,the magnetically coupled resonant physical process of grounding grid faults is solved via HFSS software.The magnetic field intensity and phase frequency characteristic curves of four mesh holes with different branches and positions of breakpoints and different corrosion degrees are studied,and an experimental system is built to verify the feasibility.The results show that under the condition of grounding grid buried depth of 0.5 m and input frequency of 1~15MHz,and there is an inverse relationship between equivalent capacitance and distortion frequency,the phase angle is positively correlated with the degree of corrosion of grounding grid,and the error of signal distortion frequency can be positioned at 5%.This paper provides some ideas for the application of magnetic coupling grounding grid detection technology.

Passive phase noise compensation for fiber-optic radio frequency transfer with a nonsynchronized source

We propose a passive compensation fiber-optic radio frequency（RF） transfer scheme with a nonsynchronized RF stable source during a round-trip time, which can avoid high-precision phase-locking and efficiently suppress the effect of backscattering only using two wavelengths at the same time. A stable frequency signal is directly reproduced by frequency mixing at the remote site. The proposed scheme is validated by the experiment over a 40 km single mode fiber spool using nonsynchronized common commercial RF sources. The influence of the stability of nonsynchronized RF sources on the frequency transfer is investigated over different length fiber links.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

Fractional-order L_βC_a filter circuit network

In this paper we introduce the new fundamentals of the conventional LC filter circuit network in the fractional domain.First, we derive the general formulae of the impedances for the conventional and fractional-order filter circuit network.Based on this, the impedance characteristics and phase characteristics with respect to the system variables of the filter circuit network are studied in detail, which shows the greater flexibility of the fractional-order filter circuit network in design.Moreover, from the point of view of the filtering property, we systematically study the effects of the filter units and fractional orders on the amplitude–frequency characteristics and phase–frequency characteristics. In addition, numerical tables of the cut-off frequency are presented. Finally, two typical examples are presented to promote the industrial applications of the fractional-order filter circuit network. Numerical simulations are presented to verify the theoretical results introduced in this paper.

DESIGN AND FABRICATION OF A 20 MHz ANNULAR ARRAY FOR MEDICAL ULTRASOUND

Most high frequency(>15MHz)medical ultrasound systems are based on single element transducers mechanically scanned.These systems can provide images with excellent resolution.However,single element transducers are often limited by the fixed focal point and small depth of field.Annular arrays consisting of concentric rings of elements are focused electronically.These arrays are desirable to avoid the fixed focal point of the single element transducers and improve the depth of field.This paper reports the design,fabrication,and characterization of a 5-element equal-area annular array transducer.After electrical impedance matching,the average center frequency was 20MHz and-6 dB bandwidths ranged from 34 to 42%.The ILs for the matched annuli ranged from 6.1 to 26.5 dB.

A NEW SCHEME FOR THE CODED SSMA SYSTEM

ＡＮＥＷＳＣＨＥＭＥＦＯＲＴＨＥＣＯＤＥＤＳＳＭＡＳＹＳＴＥＭＺｈａｎｇＱｉｎｇ（张清）ＢｉＧｕａｎｇｇｕｏ（毕光国）（ＤｅｐａｒｔｍｅｎｔｏｆＲａｄｉｏＥｎｇｉｎｅｅｒｉｎｇ）ＡＮＥＷＳＣＨＥＭＥＦＯＲＴＨＥＣＯＤＥＤＳＳＭＡＳＹＳＴＥＭ￥Ｚｈａｎ...