Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, the...Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
文摘Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
