A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.

A 12 Gbit/s limiting amplifier using 2 GaAs HBT technology for fiber-optic transmission system

A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.

A 155Mbps 0.5μm CMOS Limiting Amplifier

This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence （PRBS） input speed reaches 400Mbps.

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

Design of CMOS class-E power amplifier for low power applications

A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.

Magnetic sensitivity technology based on microwave modulation of solid state spin system NV center

In view of the low resolution and accuracy of traditional magnetometer,a method of microwave frequency modulation technology based on nitrogen-vacancy(NV)center in diamond for magnetic detection was proposed.The magnetometer studied can reduce the frequency noise of system and improve the magnetic sensitivity by microwave frequency modulation.Firstly,ESR spectra by sweeping the microwave frequency was obtained.Further,the microwave frequency modulated was gained through the mixed high-frequency sinusoidal modulation signal generated by signal generator.In addition,the frequency through the lock-in amplifier was locked,and the signal which was proportional to the first derivative of the spectrum was obtained.The experimental results show that the sensitivity of magnetic field detection can reach 17.628 nT/Hz based on microwave frequency modulation technology.The method realizes high resolution and sensitivity for magnetic field detection.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

基于电流模结构的超宽带无源混频器设计

采用SMIC 55 nm CMOS工艺,提出基于电流模结构的2~8 GHz超宽带高线性度直接下变频无源混频器结构.本设计主要结构为低噪声跨导放大器(low noise transconductance amplifier,LNTA)驱动I/Q两路电流模无源混频器,负载为低输入阻抗的跨阻放大器(trans-impedance amplifier,TIA),即LNTA-Passive Mixer-TIA结构.LNTA采用电容交叉耦合以及双端正反馈结构,解决阻抗匹配以及噪声等关键参数的折中问题.整个接收机链路获得较好的线性度及噪声性能,对于电源电压以及衬底噪声的鲁棒性也有所提升.后仿结果表明,在电源电压1.2 V情况下,射频输入信号频率为2~8 GHz,1 dB压缩点为−5.5 dBm,带内输入三阶交调点为−1 dBm,整体噪声系数为4 dB,核心版图面积为0.12 mm^(2).

基于简易实频技术的宽带高效率功率放大器设计

为了满足5G通信系统对功率放大器带宽和效率的要求,基于CGH40010F晶体管,采用简易实频技术,设计了一款工作在n77频段(3.3 GHz~4.2 GHz)的宽带高效率功率放大器。首先采用负载牵引的方法对各频点的基波最佳阻抗值以及二次谐波阻抗空间进行提取,选择简易实频技术设计宽带匹配网络,在其仿真性能良好的前提下,进行了加工测试。测试结果表明,该功率放大器在3.3 GHz~4.2 GHz频段内,漏极效率为58.1%~64.5%,增益为11.1 dB~12.9 dB,饱和输出功率为39.6 dBm~41.3 dBm。该功率放大器的性能良好,且带宽和效率具有一定的优势,可为后续宽带高效率功率放大器的设计提供参考。

基于Lushprojects虚拟实验的三极管单级放大电路教学实践

针对三极管单级放大电路教学中的重点和难点,提出了基于Lushprojects虚拟实验的教学方法。介绍了基于Lushprojects的三极管单级放大电路虚拟实验与前驱理论课程和后续线下实验课程间的关系,以及虚拟实验的导入、观察、器件和线路的调整过程等。在模拟电子技术课程教学中采用虚拟实验搭建电路,成本低、反馈及时,有助于学生快速理解和掌握影响电路性能的主要因素及相关知识点。

基于数字放大器的电容数字转换器

为了实现较高的电容检测范围,传统的采用SAR ADC的开关电容(Switched capacitor,SC)的电容数字转换器(Capacitance to digital converter,CDC)使用高压供电提高输出摆幅,而其为了保证噪声性能又采用大电流驱动,所以显著增加了系统功耗。为了解决以上问题,提出了一种基于数字放大器的电容数字转换器,将CDAC阵列作为模拟输出承担高压。仅对CDAC阵列与传感电容采用高压(5 V)驱动,而其余部分仍采用低压(1 V)供电,使得CDC在达到高动态范围与高灵敏度的同时保持低功耗、低噪声。此外,针对噪声的优化,本文一方面通过在数字放大器内加入积分环路实现SAR ADC的一阶噪声整形,降低了系统的量化噪声,提高了CDC的有效位数;另一方面通过引入有源噪声抵消(Active noise cancellation technology,ANC)技术,降低了系统的混叠噪声,提高了系统的信噪比。

基于SiGe BiCMOS的全集成射频功率放大器设计

提出了一种基于SiGe BiCMOS工艺的适用于移动设备的紧凑全集成功率放大器.设计采用cascode驱动级与共发射极功率级级联以提高放大器的功率增益,片上集成CMOS电源以提供偏置电流,采用分布式的镇流电阻和具有热负反馈效果的偏置电路补偿结温以防止放大器在高温工作时失效,并且采用一种紧凑的电路级的热耦合模型对所提出的热稳定措施进行仿真验证.后仿结果表明:PA在3.3 V供电下、2.4~2.5 GHz的工作范围内输出增益为32.5 dB,S11&S22<-10 dB,1 dB压缩点处的输出功率为25.4 dBm,在25℃的环境温度下最高结温小于65℃(饱和).芯片面积仅为1.25×0.76 mm^(2).测试结果表明:在-45~85℃的工作环境下,可以在增益要求为26.5~32.9 dB的应用中正常工作.1 dB压缩点处的输出功率为24.3 dBm.采用20 MHz 64-QAM OFDM信号测试,DEVM达到-30 dB的输出功率为18.1 dBm.

噪声系数最小1.6 dB有高带外抑制的5~6 GHz射频接收前端芯片

为了满足射频通信前端接收部分对高线性与带外信号抑制能力的要求,基于130 nm绝缘体上硅工艺设计并实现工作在5~6 GHz的射频接收前端芯片.该前端芯片由带有旁路和带外抑制功能的低噪声放大器(LNA)、射频开关和带隙基准偏置电路等组成.基于共源共栅结构的LNA,在输入匹配中使用LC陷波实现带外抑制;在偏置电路中,使用带隙基准电流源对LNA的偏置进行温度补偿,屏蔽电源纹波影响.对该前端芯片进行流片加工并测试,结果表明,当工作频率为5~6 GHz时,芯片的接收增益为13.4~14.0 dB,输入与输出反射系数均小于-10 dB,频带内的最小噪声系数为1.6 dB,在工作频率内1 dB压缩点的输入功率大于-4 dBm,输入三阶交调点大于+7 dBm.低噪声放大器在整个工作频段内无条件稳定,在2 V供电电压下电路的直流功耗为30 mW,芯片面积为0.56 mm2.

模拟电子技术基础课程中的技术思想与方法及其教育价值

技术类课程中蕴含诸多不同层面的的技术思想和方法,目前教学中尚未引起广大师生的重视,导致学生技术理解和应用的能力不强、技术素养不高。运用列举、归纳、综合的方法对模拟电子技术基础中蕴含的诸多不同层面的模拟电子技术思想和方法进行挖掘和分类概述,对教育价值进行分析。研究表明这些技术思想和方法是模拟电子技术基础的重要内容,是学生深入认识和理解、掌握和运用模拟电子技术的关键。积极挖掘并有效融入教学过程,可以提高学生模拟电子技术理解和应用能力,提升技术素养。

北斗射频功率放大器的设计与实现

深入研究了北斗射频功率放大器效率低的问题,基于射频功率放大器的基本理论,提出了射频功率放大器的基本架构,设计了三级功率放大器,采用线性功率放大器设计方案和功率回退设计方法,较好地实现了线性度和效率参数。在仿真环境下对功率放大器进行了仿真研究,验证了设计的有效性和合理性。

现代光纤通信技术在广播电视网络传输中的应用

为全面优化现代通信工程传输质量水平,共建稳定、科学及合理的信息传输通道,根据现代通信工程规范管理部署要求,全面分析光纤通信传输技术,有效发挥光纤接入、光交换以及长波单模光纤等技术的应用优势,配合发光二极管(Light Emitting Diode,LED)发射器建立更加可控的信息传输模式,利用加装光放大器的方式优化光纤通信过程的稳定性。通过完善光纤通信传输技术的应用结构,促进现代通信工程的可持续发展。因此,研究现代光纤通信技术在广播电视网络传输中的应用具有重要的实践意义。

Splicing technology of Ti:sapphire crystals for a high-energy chirped pulse amplifier laser system

We develop a splicing technology of Ti:sapphire crystals for a high-energy chirped pulse amplifier laser system that can suppress the parasitic lasing to improve the amplification efficiency compared to a large-size single Ti:sapphire crystal amplifier. Theoretical investigations on the characteristics of the amplifier with four splicing Ti:sapphire crystals,such as parasitic-lasing suppression and amplification efficiencies, are carried out. Some possible issues resulting from this splicing technology, including spectral modulation, stretching or splitting of the temporal profile, and the sidelobe generation in the spatial domain(near field and far field), are also investigated. Moreover, the feasibility of the splicing technology is preliminarily demonstrated in an experiment with a small splicing Ti:sapphire crystals amplifier. The temporal profile and spatial distribution of the output pulse from the splicing Ti:sapphire crystal amplifier are discussed in relation to the output pulse from a single Ti:sapphire crystal amplifier.

Linear Power Amplifier Modeling Based on Predistortion Technology

Different power amplifier （PA） models have their own effects on PA linearization. In this paper, the nonlinear characteristic of the radio frequency power amplifier （RF PA） is simulated based on the two models combining predistortion technology, and the nonlinear effects of the two models are analyzed, respectively. The simulation results show that Power Series model normalized mean square error （NMSE） is -37.8 dB, which is less than Power Series model -30.4 dB before loading predistortion technology. NMSE of the two systems are -23.4 dB and -26.0 dB respectively, while Saleh model compensates better than the Power Series model combing predistortion technology. The error vector magni- tude （EVM） of Power Series model is only 6.75%, whereas the Saleh model EVM is 9.99%, indicating that Power Series model can better describe the nonlinear characteristic of PA. It will have a positive effect on improving the power utilization of wireless communication system.

高速卫星通信终端数字预失真补偿技术研究

数字预失真补偿技术是解决宽带卫星系统功率、带宽资源矛盾的关键技术之一,Ka频段宽带预失真技术受器件、速率等因素限制实现难度较大。考虑记忆效应和通带非线性的等效离散Ka宽带功放建模,采用单位延迟抽头的多项式模型。宽带预失真算法采用间接学习自适应预失真算法。搭建基于宽带通用调制解调器的多项式拟合预失真验证系统,并完成实验验证。采用正交相移键控(Quadrature Phase Shift Keying,QPSK)体制,当解调损失在误码率为10-7时,比特能量噪声功率谱密度比(Eb/N0)与理论值相差1.4 dB,比未加预失真器时改善了2 dB,有效降低了功放非线性对通信信号的影响。高速卫星通信终端数字预失真补偿技术大幅降低了系统实现规模和功耗,提升了高速数据传输系统的性能,可支持星载宽带系统的设计实现。

一种新型模拟预失真线性化器

为解决氮化镓(GaN)固态功率放大器(Solid-State Power Amplifier, SSPA)线性度较差的问题,采用模拟预失真技术设计了一款新型结构的线性化器,将2支肖特基二极管及其管座电路并联,并通过2路偏置电路分别控制,使用微带隔离器减少二极管间的相互干扰,并对输入输出驻波进行改善。通过电路设计软件ADS进行仿真,仿真结果显示,可以实现幅度补偿2.2~6.1 dB,相位补偿21.5°~49°。根据测试数据建立功率放大器非线性模型,与线性化器进行级联仿真。结果表明,目标GaN SSPA饱和输出功率回退3 dB时,可改善三阶互调10 dB以上。进行实物加工及测试,验证了该线性化器可大幅改善功率放大器的线性度。