We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for...Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.展开更多
为了抑制机车四象限脉冲整流器在网侧产生的高频谐波,防止车网发生高次谐波共振,提出一种基于二阶广义积分器锁相环SOGI-PLL(second-order generalized integral phase-locked loop)载波移相控制策略。将锁相环输出的电网相位作为同步...为了抑制机车四象限脉冲整流器在网侧产生的高频谐波,防止车网发生高次谐波共振,提出一种基于二阶广义积分器锁相环SOGI-PLL(second-order generalized integral phase-locked loop)载波移相控制策略。将锁相环输出的电网相位作为同步基准信号,针对网压频率异常波动,快速同步校正PWM载波周期,保证了各单元之间移相角的准确性,获得最优谐波对消效果。同时,该策略对电网谐波和幅值异常跳变不敏感,具有良好的抗干扰性和自适应性。最后通过半实物仿真和地面联调试验,验证了该策略的可行性和对谐波抑制的有效性。展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
同步参考坐标系锁相环是高压直流(high voltage direct current,HVDC)同步触发控制系统中广泛应用的一种窄带宽锁相环,在交流系统故障引起相位跳变情况下,其动态响应缓慢。为增大锁相环的带宽,一种滑动平均滤波器(moving average filter...同步参考坐标系锁相环是高压直流(high voltage direct current,HVDC)同步触发控制系统中广泛应用的一种窄带宽锁相环,在交流系统故障引起相位跳变情况下,其动态响应缓慢。为增大锁相环的带宽,一种滑动平均滤波器(moving average filter,MAF)被前置于锁相环路,然而MAF本身存在响应延迟,制约了锁相环的同步速度。为了缓解响应延迟问题,文中提出一种考虑MAF延时和前馈补偿的HVDC快速锁相环。首先,利用MAF线性暂态特征预测相位变化,并分别针对故障接入和切除引起的相位跳变问题提出不同的补偿策略;接着,利用不变性原理对锁相环路进行前馈补偿,在负反馈控制和前馈补偿共同构成的复合校正控制系统的作用下,锁相环能够在较小PI参数下实现快速响应;最后,将所提快速锁相环在CIGRE HVDC标准模型和三峡—上海直流工程模型中进行仿真验证。结果表明,该快速锁相环能够有效缓解滤波器响应延迟的制约,缩短失锁时间,进而提高高压直流逆变侧抵御换相失败的能力。展开更多
Chirp超宽带具有峰值平均功率比(peak to average power ratio,PAPR)接近为1、测距定位能力强等优势,能够有效解决传统的超宽带技术存在的PAPR过大、传输距离短等问题,设计并产生Chirp超宽带信号是实现该通信系统的关键技术之一。提出...Chirp超宽带具有峰值平均功率比(peak to average power ratio,PAPR)接近为1、测距定位能力强等优势,能够有效解决传统的超宽带技术存在的PAPR过大、传输距离短等问题,设计并产生Chirp超宽带信号是实现该通信系统的关键技术之一。提出了一种高性能Chirp超宽带信号源方案,通过采用现场可编程门阵列(field-programma-ble gate array,FPGA)控制直接数字频率合成(direct digital synthesis,DDS)芯片AD9956产生低频Chirp信号,并结合锁相环(phase locked loop,PLL)技术实现带宽扩展,从而获得Chirp超宽带信号。实验表明,所设计的Chirp超宽带信号源具有结构简单、可编程、可扩展、性能好及实用性强等优点。展开更多
快速准确的锁相环技术是保证并网系统安全、可靠并网的关键。针对传统EPLL的固有缺陷,设计了一种改进型EPLL算法,适用于以分布式电源为主的微网并网控制技术。首先,推导出输出电压频率和输入电压幅值之间的耦合关系,使用数学公式进行近...快速准确的锁相环技术是保证并网系统安全、可靠并网的关键。针对传统EPLL的固有缺陷,设计了一种改进型EPLL算法,适用于以分布式电源为主的微网并网控制技术。首先,推导出输出电压频率和输入电压幅值之间的耦合关系,使用数学公式进行近似解耦。其次,搭建误差信号的成本函数,利用梯度下降法设计直流偏移量的估算环路,通过闭环负反馈回路消去输入信号中的直流偏置。然后,在锁相算法的所有估算环路中引入滑动平均值滤波器MAF(moving average filter),以增强控制系统的高频谐波抗干扰能力。最后,在Matlab/Simulink软件中搭建了单相锁相环算法的仿真模型,进行对比分析。仿真结果验证了所提算法的正确性和可行性。展开更多
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
基金Supported by the National Natural Science Foundation of China (No. 61106024, 60901012, 60976029) , the National High Technology Research and Development Program of China (No. 2011AA010301 ), and the Science and Technology Program of Southeast University (No. K J2010402 ).
文摘Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.
文摘为了抑制机车四象限脉冲整流器在网侧产生的高频谐波,防止车网发生高次谐波共振,提出一种基于二阶广义积分器锁相环SOGI-PLL(second-order generalized integral phase-locked loop)载波移相控制策略。将锁相环输出的电网相位作为同步基准信号,针对网压频率异常波动,快速同步校正PWM载波周期,保证了各单元之间移相角的准确性,获得最优谐波对消效果。同时,该策略对电网谐波和幅值异常跳变不敏感,具有良好的抗干扰性和自适应性。最后通过半实物仿真和地面联调试验,验证了该策略的可行性和对谐波抑制的有效性。
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
文摘同步参考坐标系锁相环是高压直流(high voltage direct current,HVDC)同步触发控制系统中广泛应用的一种窄带宽锁相环,在交流系统故障引起相位跳变情况下,其动态响应缓慢。为增大锁相环的带宽,一种滑动平均滤波器(moving average filter,MAF)被前置于锁相环路,然而MAF本身存在响应延迟,制约了锁相环的同步速度。为了缓解响应延迟问题,文中提出一种考虑MAF延时和前馈补偿的HVDC快速锁相环。首先,利用MAF线性暂态特征预测相位变化,并分别针对故障接入和切除引起的相位跳变问题提出不同的补偿策略;接着,利用不变性原理对锁相环路进行前馈补偿,在负反馈控制和前馈补偿共同构成的复合校正控制系统的作用下,锁相环能够在较小PI参数下实现快速响应;最后,将所提快速锁相环在CIGRE HVDC标准模型和三峡—上海直流工程模型中进行仿真验证。结果表明,该快速锁相环能够有效缓解滤波器响应延迟的制约,缩短失锁时间,进而提高高压直流逆变侧抵御换相失败的能力。
文摘Chirp超宽带具有峰值平均功率比(peak to average power ratio,PAPR)接近为1、测距定位能力强等优势,能够有效解决传统的超宽带技术存在的PAPR过大、传输距离短等问题,设计并产生Chirp超宽带信号是实现该通信系统的关键技术之一。提出了一种高性能Chirp超宽带信号源方案,通过采用现场可编程门阵列(field-programma-ble gate array,FPGA)控制直接数字频率合成(direct digital synthesis,DDS)芯片AD9956产生低频Chirp信号,并结合锁相环(phase locked loop,PLL)技术实现带宽扩展,从而获得Chirp超宽带信号。实验表明,所设计的Chirp超宽带信号源具有结构简单、可编程、可扩展、性能好及实用性强等优点。
文摘快速准确的锁相环技术是保证并网系统安全、可靠并网的关键。针对传统EPLL的固有缺陷,设计了一种改进型EPLL算法,适用于以分布式电源为主的微网并网控制技术。首先,推导出输出电压频率和输入电压幅值之间的耦合关系,使用数学公式进行近似解耦。其次,搭建误差信号的成本函数,利用梯度下降法设计直流偏移量的估算环路,通过闭环负反馈回路消去输入信号中的直流偏置。然后,在锁相算法的所有估算环路中引入滑动平均值滤波器MAF(moving average filter),以增强控制系统的高频谐波抗干扰能力。最后,在Matlab/Simulink软件中搭建了单相锁相环算法的仿真模型,进行对比分析。仿真结果验证了所提算法的正确性和可行性。