Bandwidth Design for CMOS Monolithic Photoreceiver

A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth design method of a monolithic photoreceiver is presented.An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail.A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0.6μm CMOS process and the test result is given.

Design and Analysis of Analog Front-End of Passive RFID Transponders

An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.

A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.

Low-power SiPM readout BETA ASIC for space applications

The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.

Patent Information Analysis of Front-end Industry Chain in China's Tobacco Industry

The research performed analysis on patent applicant ranking, IPC, patent type and legal status in order to explore application and authorization of front-end industry chain dominated by planting, breeding, soil improvement and substrate culti- vation technologies. The results showed that research institutions and big tobacco enterprises play a leading role in the tobacco industry, for example, Yunnan Tobac- co Agricultural S＆T Research Institute and Guizhou Tobacco Agricultural S＆T Re- search Institute have a total of 26 patents; A01G subclass represents 58% of total patents, dominated by Yunnan Tobacco Agricultural S＆T Research Institute and Henan Agricultural University; there are only invention and practical use patents, of which invention patents represent 92%; authorized patents take up to 31% and in- valid patents represent 23%.

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

A Low Noise,1.25Gb/s Front-End Amplifier for Optical Receivers

This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.

Multi-frequency point supported LLRF front-end for CiADS wide-bandwidth application

The China initiative Accelerator Driven System,CiADS,physics design adopts 162.5 MHz,325 MHz,and 650 MHz cavities,which are driven by the corresponding radio frequency(RF)power system,requiring frequency translation front-end for the RF station.For that application,a general-purpose design front-end prototype has been developed to evaluate the multi-frequency point supported design feasibility.The difficult parts to achieve the requirements of the general-purpose design are reasonable device selection and balanced design.With a carefully selected low-noise wide-band RF mixer and amplifier to balance the performance of multi-frequency supported down-conversion,specially designed LO distribution net to increase isolation between adjacent channels,and external band-pass filter to realize expected up-conversion frequencies,high maintenance and modular front-end generalpurpose design has been implemented.Results of standard parameters show an R2 value of at least 99.991%in the range of-60-10 dBm for linearity,up to 18 dBm for P1dB,and up to 89 dBc for cross talk between adjacent channels.The phase noise spectrum is lower than 80 dBc in the range of 0-1 MHz;cumulative phase noise is 0.006°;and amplitude and phase stability are 0.022%and 0.034°,respectively.

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) trans- ponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD) protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

This paper presents efficient processing engines for software-defined radio （SDR） front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filterbank （where the number of data loads is not equal to the number of M subfilters） processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resamp/ing in SDR front-ends. These modes are （i） maximally decimated, （ii） Under-decimated, （iii） over-decimated, and combined up- and down-sampling with （iv） single stride length, and （v） multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates.

A single-ended wideband reconfigurable receiver front-end for multi-mode multi-standard applications in 0.18μm CMOS

This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.

Design of a Low-Noise Front-End Readout CSP-Shaper System for CZT Detectors

This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

A tunable passive mixer for SAW-less front-end with reconfigurable voltage conversion gain and intermediate frequency bandwidth

An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.

The front-end electronics design of dose monitors for beam delivery system of Shanghai Advanced Proton Therapy Facility

A front-end electronics of dose monitor has been developed for measuring irradiation dose to the patient in Shanghai Advanced Proton Therapy Facility.The parallel plate ionization chamber is used for the dose monitoring.Unlike the traditional method of recycling capacitor integration and voltage-to-frequency conversion,this dose monitor electronics uses the trans-impedance amplifier and analog-to-digital conversion method.It performs satisfactorily,with the integral nonlinearity of less than ±0.04 nA in the range of-400 to 50 nA and the resolution of about±0.6 nA.

Study of Reducing Non-Ideal Effects Based on TiN Sensitive Electrode with Front-End Offset Circuit

The structure of the extended gate ion sensitive field effect transistor (EGISFET) is similar to the structure of the ion sensitive field effect transistor (ISFET).Moreover,the non-ideal effect of EGISFET is the main impediment to development of commercial processes for sensitive devices.It is necessary to promote the stability and reliability of the devices by employing calibration circuits and the better fabrication conditions.The temporal drift exists in the entire measurement experiment. Furthermore,in this study we can reduce the temporal drift effect which influences the stability of the TiN sensitive electrode with the differential front-end offset circuit.The measurement system combines with shifting circuit,differential and instrument amplifiers.We employ the calibration circuit to compare with the variations of the output voltage,and expectably improve the stability and reliability of the TiN sensitive electrode by the novel calibration circuit.

Front-end Control Mechanism of Electronic Records

In the digital era,how to ensure the authenticity and integrity of elec-tronic records has become an open challenging issue.Front-end control is an important concept as well as a basic principle in electronic record management.Under the instruction of front-end control,many original management links in the record-management stage are required to move forward,and the managers enter the formation stage of the electronic records to ensure the originality.How-ever,the front-end control technique primarily focuses on transaction manage-ment,and it lacks the strategy of providing the control of electronic records.In this paper,a novel electronic record front-end control mechanism is proposed by adopting proxy re-encryption and requiring archivists to participate in the man-agement of electronic records before the record is created to solve the problem.Specifically,when an electronic record is generated,the proposed mechanism interacts with the producer of the electronic record to generate a corresponding encryption key.Moreover,electronic records are encrypted by the key to protect their confidentiality,which can prevent the leakage of electronic record informa-tion.In addition,when transferring the electronic record,archivists use proxy re-encryption technology to convert electronic records,allowing management by an archivist,ensuring their originality and authenticity.

An Antenna Diversity Scheme for Digital Front-End with OFDM Technology

In,this paper, we propose a new antenna diversity scheme for OFDM-based wireless communication and digital broadcasting applications. Compared with existing schemes, such as post-fast Fourier transform （FFT）, pre-FFT, and polyphase-based fitter-bank, the proposed scheme performs optimally and has very low computational complexity. It offers a better compromise between performance, power consumption, and complexity in real-time implementation of the receivers of broadband communication and digital broadcasting systems.

Transforming Hand Drawn Wireframes into Front-End Code with Deep Learning

The way towards generating a website front end involves a designersettling on an idea for what kind of layout they want the website to have, thenproceeding to plan and implement each aspect one by one until they haveconverted what they initially laid out into its Html front end form, this processcan take a considerable time, especially considering the first draft of the designis traditionally never the final one. This process can take up a large amountof resource real estate, and as we have laid out in this paper, by using a Modelconsisting of various Neural Networks trained on a custom dataset. It can beautomated into assisting designers, allowing them to focus on the other morecomplicated parts of the system they are designing by quickly generating whatwould rather be straightforward busywork. Over the past 20 years, the boomin how much the internet is used and the sheer volume of pages on it demands ahigh level of work and time to create them. For the efficiency of the process, weproposed a multi-model-based architecture on image captioning, consisting ofConvolutional neural network (CNN) and Long short-term memory (LSTM)models. Our proposed approach trained on our custom-made database can beautomated into assisting designers, allowing them to focus on the other morecomplicated part of the system. We trained our model in several batches overa custom-made dataset consisting of over 6300 files and were finally able toachieve a Bilingual Evaluation Understudy (BLEU) score for a batch of 50hand-drawn images at 87.86%.

Advances in Digital Front-End and Software RF Processing: PartⅡ

In the first editorial of this two-part special issue, we pointed out that one of the biggest trends in wireless broadband, radar, sonar, and broadcasting technology is software RF processing and digital front-end [1]. Thistrend encompasses signal processing algorithms and integrated circuit design and includes digital pre-distortion （DPD）, conversions between digital and analog signals, digita up-conversion （DUC）, digital down-conversion （DDC）, DC offset,

A Broadband T/R Front-End of Millimeter Wave Holographic Imaging

A broadband T/R frond-end of active holographic imaging system is presented. Compact autodyne mode circuit structure front-end is adopted to achieve higher signal to noise ratio and higher reliability, which is beneficial to the after-end imagining. The factors that influence the dynamic range and the transverse resolution ratio of holographic imaging system have been analyzed. Wide-band oscillator, wide-band low noise amplifier and the tapered slot antennas are implemented to meet the requirements of the holographic imagining system. According to the measured results, the output power is uniform in the broadband working frequency. The sub-harmonic suppression is better than 25 dBc from the frequency of 28 GHz to 33 GHz. The isolation between antennas channel is greater than 20 dB. The experimental result shows that the performance of the front-end is good enough to meet the needs of active millimeter-wave holographic imaging system.