A quantum efficiency analytical model for complementary metal–oxide–semiconductor image pixels with a pinned photodiode structure

A quantum efficiency analytical model for complementary metal–oxide–semiconductor（CMOS） image pixels with a pinned photodiode structure is developed. The proposed model takes account of the non-uniform doping distribution in the N-type region due to the impurity compensation formed by the actual fabricating process. The characteristics of two boundary PN junctions located in the N-type region for the particular spectral response of a pinned photodiode, are quantitatively analyzed. By solving the minority carrier steady-state diffusion equations and the barrier region photocurrent density equations successively, the analytical relationship between the quantum efficiency and the corresponding parameters such as incident wavelength, N-type width, peak doping concentration, and impurity density gradient of the N-type region is established. The validity of the model is verified by the measurement results with a test chip of 160×160 pixels array,which provides the accurate process with a theoretical guidance for quantum efficiency design in pinned photodiode pixels.

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.

Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure

A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson＇s equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.

Photoelectric characteristics of an inverse U-shape buried doping design for crosstalk suppression in pinned photodiodes

A design of an inverse U-shape buried doping in a pinned photodiode （PPD） of CMOS image sensors is proposed for electrical crosstalk suppression between adjacent pixels. The architecture achieves no extra fill factor consumption, and proper built-in electric fields can be established according to the doping gradient created by the injections of the extremely low P-type doping buried regions in the epitaxial layer, causing the excess electrons to easily drift back to the photosensitive area rarely with a diffusion probability; the overall junction capacitance and photosensitive area extensions for a full well capacity （FWC） and internal quantum efficiency （IQE） improving are achieved by the injection of a buried N-type doping. By considering the image lag issue, the process parameters of all the injections have been precisely optimized. Optical simulation results based on the finite difference time domain method show that compared to the conventional PPD, the electrical crosstalk rate of the proposed architecture can be decreased by 60%-80% at an incident wavelength beyond 450 nm, IQE can be clearly improved at an incident wavelength between 400 and 600 nm, and the FWC can be enhanced by 107.5%. Furthermore, the image lag performance is sustained to a perfect low level. The present study provides important guidance on the design of ultra high resolution image sensors.

The Effects by γ Ray Irradiation on Silicon Photodiodes

The relationships between irradiation doses of γ ray and the main photoelectric characteristics of PIN photodiode or conventional photodiode with different structure were studied. The experimental results show that after the photodiodes being irradiated,the photocurrent decreases,especially for short wavelength of light. The dark current of the photodiodes with smaller active area decreases while increases for that with larger active area,and the response time shortens. The plane scanning experiment of laser beam indicates that the homogeneity of the device's surface is not influenced by the irradiation. The results prove that PIN photodiode shows relatively good radioresistance.

Silicon PIN photodiode applied to acquire high-frequency sampling XAFS spectra

Experimental techniques based on SR facilities have emerged with the development of synchrotron radiation(SR)sources.Accordingly,detector miniaturization has become significant for the development of SR experimental techniques.In this study,the miniaturization of a detector was achieved by coupling a commercial silicon PIN photodiode(SPPD)into a beamstop,aiming for it not only to acquire X-ray absorption fine structure(XAFS)spectra,but also to protect the subsequent two-dimensional detector from high-brilliance X-ray radiation damage in certain combination techniques.This mini SPPD detector coupled to a beamstop was used as the rear detector in both the conventional sampling scheme and novel high-frequency(HF)sampling scheme to collect the transmission XAFS spectra.Traditional ion chambers were also used to collect the transmission XAFS spectra,which were used as the reference.These XAFS spectra were quantitatively analyzed and compared;the results demonstrated that the XAFS spectra collected by this SPPD in both the conventional sampling scheme and HF sampling scheme are feasible.This study provides a new detector-selection scheme for the acquisition of the quick-scanning XAFS(QXAFS)and HF sampling XAFS spectra.The SPPD detector presented in this study can partially meet the requirements of detector miniaturization.

Scalability of dark current in silicon PIN photodiode

The mechanism for electrical conduction is investigated by the dark temperature-dependent current–voltage characteristics of Si PIN photodiodes with different photosensitive areas.The characteristic tunneling energy E（00） can be obtained to be 1.40 me V,1.53 me V,1.74 me V,1.87 me V,and 2.01 me V,respectively,for the photodiodes with L = 0.25 mm,0.5 mm,1 mm,1.5 mm,and 2 mm by fitting the ideality factor n versus temperature curves according to the tunneling-enhanced recombination mechanism.The trap-assisted tunneling-enhanced recombination in the i-layer plays an important role in our device,which is consistent with the experimental result that area-dependent leakage current is dominant with the side length larger than 1 mm of the photosensitive area.Our results reveal that the quality of the bulk material plays an important role in the electrical conduction mechanism of the devices with the side length larger than 1 mm of the photosensitive area.

Novel CMOS image sensor pixel to improve charge transfer speed and efficiency by overlapping gate and temporary storage diffusing node

A novel CMOS image sensor(CIS) pinned photodiode(PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping gate(OG)and the temporary storage diffusing(TSD) region, based on which the several-nanosecond-level charge transfer could be achieved and the complete charge transfer from the PPD to the floating node(FD) could be realized. And systematic analyses of the influence of the doping conditions of the proposed processes, the OG length, and the photodiode length on the transfer performances of the proposed pixel are conducted. Optimized simulation results show that the total charge transfer time could reach about 5.862 ns from the photodiode to the sensed node and the corresponding charge transfer efficiency could reach as high as 99.995% in the proposed pixel with 10 μm long photodiode and 2.22 μm long OG. These results demonstrate a great potential of the proposed pixel in high-speed applications.

Frequency Response Optimization of Dual Depletion InGaAs/InP PIN Photodiodes

The frequency response of a dual depletion p-i-n （PIN） photodiode structure is investigated. It is assumed that the light is incident on the N side and the drift region is located between the N contact and the absorption region. The numerical model takes into account the transit time and the capacitive effects and is applied to photodiodes with non-uniform illumination and linear electric field profile. With an adequate choice of the device＇s structural parameters, dual depletion photodiodes can have larger bandwidths than the conventional PIN devices.

Process techniques of charge transfer time reduction for high speed CMOS image sensors

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode （PPD） and the voltage difference between the PPD and the floating diffusion （FD） node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

Analysis of incomplete charge transfer effects in a CMOS image sensor

Abs A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction. Further analysis of noise for incomplete charge transfer predicts the noise variation. The test pixels were fabricated in a specialized 0.18 #m CMOS image sensor process and two different processes of buried N layer implantation are compared. The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer. The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.