A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.

A 16 bit Stereo Audio ΣΔ A/D Converter

A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.

PIPELINED多值A/D转换器

通过对多值ADC数学表示的分析，指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论，设计了Pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。

Pipelined-Flash A/D转换误差分布规律

本文讨论参考文献[1]中两类四元非线性连续函数△ERRdn与△ERRdj之间的定量关系,对误差比率函数ERR100nm%(λcentreT,n)离散点域分布演变所起的决定性作用。定性地归纳各类误差离散点域的分布变化规律,为推出分时段并行A/D转换电路的各种可变参量裕度函数作好准备。

Numeric Simulation of Single Passage Ternary Turbulence Model in Hydraulic Torque Converter

Based on the renormalization group theory, a hydraulic torque converter 3 D turbulent single flow passage model is constructed and boundary condition is determined for analyzing the influence of the fluid field characteristic and parameters on the macroscopic model. Numerical simulation of the single fluid path is processed by computational fluid dynamics and the calculated results approach to experimental data well, and especially in low transmission ratio the torque and head results are more close to experimental data than the calculated results of beam theory. This shows that the appropriate ternary analysis method and reasonable assumption of boundary condition may analyze the flow field more precisely and predict the performance of torque converter more accurately.

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

A 10bit 2GHz CMOS D/A Converter for High-Speed System Applications

This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.

Performance Optimization of Torque Converters Based on Modified 1D Flow Model

A methodology for performance optimization of torque converters is put forward based on the one-dimensional (1D) flow model. It is found that the inaccuracy of 1D flow model for predicting hydraulic performance at the low speed ratio is mainly caused by the separation phenomenon at the stator cascade which is induced by large flow impinging at the pressure side of the stator blades. A semi-empirical separation model is presented and incorporated to the original 1D flow model. It is illustrated that the improved model is able to predict the circumferential velocity components accurately, which can be applied to performance optimization. Then, the Pareto front is obtained by using the genetic algorithm (GA) in order to inspect the coupled relationship among stalling impeller torque capacity, stalling torque ratio and efficiency. The efficiency is maximized on the premise that a target stalling impeller torque capacity and torque ratio are achieved. Finally, the optimized result is verified by the computational fluid dynamics(CFD) simulation, which indicates that the maximal efficiency is increased by 0.96%.

Numerical simulation of the flow field of a flat torque converter

A flexible flat torque converter was proposed to fulfill the requirement of miniaturization and power density maximization for automobiles.Constructed by two arcs joined by lines,the torus was designed directly from design path.The influence of flatness on the performance of the torque converter was evaluated.The software CFX and standard k-ε model were adopted to simulate the internal flow fields of the torque converter under different flatness ratios.The results indicated that the performance of the torque converter got worse as the flatness declined,but the capacity of pump increased.The efficiency and the torque ratio dropped slightly as the flatness ratio decreased.So the torque converter could be squashed appropriately to get high power density without too much efficiency sacrifice.But when the flatness ratio was below 0.2,there was a significant drop in the efficiency.

Analytical Modelling and Experiment of Novel Rotary Electro-Mechanical Converter with Negative Feedback Mechanism for 2D Valve

The manufacturing of spiral groove structure of two-dimensional valve(2D valve)feedback mechanism has shortcomings of both high cost and time-consuming.This paper presents a novel configuration of rotary electro-mechanical converter with negative feedback mechanism(REMC-NFM)in order to replace the feedback mechanism of spiral groove and thus reduce cost of valve manufacturing.In order to rapidly and quantitative evaluate the driving and feedback performance of the REMC-NFM,an analytical model taking leakage flux,edge effect and permeability nonlinearity into account is formulated based on the equivalent magnetic circuit approach.Then the model is properly simplified in order to obtain the optimal pitch angle.FEM simulation is used to study the influence of crucial parameters on the performance of REMC-NFM.A prototype of REMC-NFM is designed and machined,and an exclusive experimental platform is built.The torque-angle characteristics,torque-displacement characteristics,and magnetic flux density in the working air gap with different excitation currents are measured.The experimental results are in good agreement with the analytical and FEM simulated results,which verifies the correctness of the analytical model.For torque-angle characteristics,the overall torque increases with both current and rotation angle,which reaches about 0.48 N·m with 1.5 A and 1.5°.While for torque-displacement characteristics,the overall torque increases with current yet decrease with armature displacement due to the negative feedback mechanism,which is about 0.16 N·m with 1.5 A and 0.8 mm.Besides,experimental results of conventional torque motor are compared with counterparts of REMC-NFM in order to validate the simplified model.The research indicates that the REMC-NFM can be potentially used as the electro-mechanical converter for 2D valves in civil servo areas.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

基于g_(m)/I_(d)方法的Pipelined-SAR ADC高性能余量放大器设计

基于g_(m)/I_(d)查找表方法,设计了一种用于14位100MS/s流水线逐次逼近寄存器模数转换器(Pipelined-SAR ADC)的余量放大器。该余量放大器采用高增益宽带宽的增益自举运算放大器(OTA)结构。该方法通过lookup函数查找器件直流工作点,克服了传统方法对短沟道器件参数无法准确设计的问题。通过迭代算法来选择核心器件的g_(m)/I_(d),使电路在满足性能要求的同时实现功耗的优化设计,且具有很好的工艺移植性。基于SMIC 55nm CMOS工艺,对设计的OTA性能进行了仿真验证,实现了在92dB直流增益、180MHz闭环-3dB带宽、1.44mVrms噪声等多维约束条件下电路功耗为1.9mW的最优化设计。

The Design of A/D Converter Circuit Adopting the Technology of PWM

This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithmetic and relevant program design arediscussed in detail. And it has analyzed the resolution of A/D converter based on the technology of PWM, etc.

基于D-分割法的直流变换器遗传自抗扰控制器设计

针对光伏发电系统中DC-DC变换器由于负载和工作环境条件变化等扰动引起的输出波动问题,提出一种基于D-分割法的直流变换器遗传自抗扰控制器(ADRC)设计方法。该方法适用于设计光伏发电领域中的双向DC-DC变换器,采用D-分割法获得满足闭环系统鲁棒稳定的ADRC控制器参数范围;利用具有全局寻优能力的遗传算法,按综合性能指标在该范围内进行参数寻优。实验结果表明,所提基于D-分割法的直流变换器遗传自抗扰控制器设计方法能有效抑制微网母线侧的电压波动和负载突变,提高控制器的鲁棒性,增强光伏发电系统的动态响应性能和抗干扰能力。

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。

Building Information Modeling-Based Secondary Development System for 3D Modeling of Underground Pipelines

Underground pipeline networks constitute a major component of urban infrastructure,and thus,it is imperative to have an efficient mechanism to manage them.This study introduces a secondary development system to efficiently model underground pipeline networks,using the building information modeling(BIM)-based software Revit.The system comprises separate pipe point and tubulation models.Using a Revit application programming interface(API),the spatial position and attribute data of the pipe points are extracted from a pipeline database,and the corresponding tubulation data are extracted from a tubulation database.Using the Family class in Revit API,the cluster in the self-built library of pipe point is inserted into the spatial location and the attribute data is added;in the same way,all pipeline instances in the pipeline system are created.The extension and localization of the model accelerated the modeling speed.The system was then used in a real construction project.The expansion of the model database and rapid modeling made the application of BIM technology in three-dimensional visualization of underground pipeline networks more convenient.Furthermore,it has applications in pipeline engineering construction and management.

Discussion on applying an analytical method to optimize the anti-freeze design parameters for underground water pipelines in seasonally frozen areas

Adopting the quasi-three-dimensional （Quasi-3D） numerical method to optimize the anti-freeze design parameters of an underground pipeline usually involves heavy numerical calculations. Here, the fitting formulae between the safe con-veyance distance （SCD） of a water pipeline and six influencing factors are established based on the lowest water temper-ature （LWT） along the pipeline axis direction. With reference to the current widely used anti-freeze design approaches for underground pipelines in seasonally frozen areas, this paper first analyzes the feasibility of applying the maximum frozen penetration （MFP） instead of the mean annual ground surface temperature （MAGST） and soil water content （SWC） to calculate the SCD. The results show that the SCD depends on the buried depth if the MFP is fixed and the variation of the MAGST and SWC combination does not significantly change the SCD. A comprehensive formula for the SCD is estab-lished based on the relationships between the SCD and several primary influencing factors and the interaction among them. This formula involves five easy-to-access parameters： the MFP, buried depth, pipeline diameter, flow velocity, and inlet water temperature. A comparison between the analytical method and the numerical results based on the Quasi-3D method indicates that the two methods are in good agreement overall. The analytic method can be used to optimize the anti-freeze design parameters of underground water pipelines in seasonally frozen areas under the condition of a 1.5 safety coefficient.

A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs

The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.