Aim To design an ASIC based on CORDIC(coordinate rotations digital computer) to meet the requirement of coordinate conversion in high speed radar signal processing. Methods A new pipeline CORDIC architecture easi...Aim To design an ASIC based on CORDIC(coordinate rotations digital computer) to meet the requirement of coordinate conversion in high speed radar signal processing. Methods A new pipeline CORDIC architecture easily realized in VLSI was introduced. Results and Conclusion The results of hardware simulation with FPGA show that the pipeline CORDIC architecture meets the requirement.展开更多
This paper presented a new solution for motion compensation module in the high definition television (HDTV) video decoder. The overall architecture and the design of the major functional units, such as the motion vect...This paper presented a new solution for motion compensation module in the high definition television (HDTV) video decoder. The overall architecture and the design of the major functional units, such as the motion vector decoder, the predictor, and the mixer, were discussed. Based on the exploitation of the special characteristics inherent in the motion compensation algorithm, the motion compensation module and its functional units adopt various novel architectures in order to allow the module to meet real-time constraints. This solution resolves the problem of high hardware costs, low bus efficiency and complex control schemes in conventional designs.展开更多
文摘Aim To design an ASIC based on CORDIC(coordinate rotations digital computer) to meet the requirement of coordinate conversion in high speed radar signal processing. Methods A new pipeline CORDIC architecture easily realized in VLSI was introduced. Results and Conclusion The results of hardware simulation with FPGA show that the pipeline CORDIC architecture meets the requirement.
文摘This paper presented a new solution for motion compensation module in the high definition television (HDTV) video decoder. The overall architecture and the design of the major functional units, such as the motion vector decoder, the predictor, and the mixer, were discussed. Based on the exploitation of the special characteristics inherent in the motion compensation algorithm, the motion compensation module and its functional units adopt various novel architectures in order to allow the module to meet real-time constraints. This solution resolves the problem of high hardware costs, low bus efficiency and complex control schemes in conventional designs.
