过电平模数转换器采用异步采样的方式进行数据转换.主要对转换器的不同时间模式进行了研究,综合分析了误差源对异步采样ADC性能的影响,特别对有限时间分辨率、有限精度量化两种主要误差源进行了详细分析.通过优化设计,将计算采样时刻的...过电平模数转换器采用异步采样的方式进行数据转换.主要对转换器的不同时间模式进行了研究,综合分析了误差源对异步采样ADC性能的影响,特别对有限时间分辨率、有限精度量化两种主要误差源进行了详细分析.通过优化设计,将计算采样时刻的最大量化误差降为计数器时钟周期的一半,有效提高了系统的信噪比(SNR).推导出SNR的方程,对于固定的时钟频率,当量化分辨率较大时,SNR达到62 d B左右.通过仿真确认了方程的正确性.展开更多
This paper presents a 50 Hz 15-bit analog-to-digital converter （ADC） for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject c...This paper presents a 50 Hz 15-bit analog-to-digital converter （ADC） for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets. The core circuit for charge/pulse conversion is specially optimized for low power, low noise and small area. An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification. The measurement result shows a standard deviation of 1.8 LSB for full-scale output. The ADC has an area of 45 × 45μm^2 and consumes less than 2 μW in a standard 1P-6M 0.18μm CMOS process.展开更多
A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design ...A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.展开更多
文摘过电平模数转换器采用异步采样的方式进行数据转换.主要对转换器的不同时间模式进行了研究,综合分析了误差源对异步采样ADC性能的影响,特别对有限时间分辨率、有限精度量化两种主要误差源进行了详细分析.通过优化设计,将计算采样时刻的最大量化误差降为计数器时钟周期的一半,有效提高了系统的信噪比(SNR).推导出SNR的方程,对于固定的时钟频率,当量化分辨率较大时,SNR达到62 d B左右.通过仿真确认了方程的正确性.
基金supported by the Major National Science & Technology Program of China(No.2012ZX03004004-002)
文摘This paper presents a 50 Hz 15-bit analog-to-digital converter （ADC） for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets. The core circuit for charge/pulse conversion is specially optimized for low power, low noise and small area. An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification. The measurement result shows a standard deviation of 1.8 LSB for full-scale output. The ADC has an area of 45 × 45μm^2 and consumes less than 2 μW in a standard 1P-6M 0.18μm CMOS process.
基金supported by the National Natural Science Foundation of China(Nos.60676009,60725415,60776034,60803038)the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260).
文摘A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
