For an SOI-FPGA （silicon-on-insulator field programmable gate arrays） （VS1000） fabricated with 0.5 ttm SOI-CMOS （silicon-on-insulator complementary-metal-oxide-semiconductor） process, a complete integrated platf...For an SOI-FPGA （silicon-on-insulator field programmable gate arrays） （VS1000） fabricated with 0.5 ttm SOI-CMOS （silicon-on-insulator complementary-metal-oxide-semiconductor） process, a complete integrated platform of FPGA computer-aided design （CAD） toolset （VDK） is developed, which can convert the Verilog HDL （hardware description language） description into a bitstream and finally download it into an FPGA. Experiments and testing verify that this FPGA CAD works well and efficiently.展开更多
According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analy...According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.展开更多
文摘For an SOI-FPGA （silicon-on-insulator field programmable gate arrays） （VS1000） fabricated with 0.5 ttm SOI-CMOS （silicon-on-insulator complementary-metal-oxide-semiconductor） process, a complete integrated platform of FPGA computer-aided design （CAD） toolset （VDK） is developed, which can convert the Verilog HDL （hardware description language） description into a bitstream and finally download it into an FPGA. Experiments and testing verify that this FPGA CAD works well and efficiently.
基金supported by the National High Technology Research and Development Program of China ("863" Program) (Grant No. 2006SQ710375)the Civil Aerospace Technologies Advanced Research Pro-gram of China (Grant No. C1320061301)Ministries and Commissions’Advanced Research Found of China (Grant No. 9140A20070209KG0160)
文摘According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.
