Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.

SEGR-and SEB-hardened structure with DSPSOI in power MOSFETs

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOS- FETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator （DSPSOI） layers. Results show that the safety operation area （SOA） of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV-cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.

Charge deposition model for investigating SE-microdose effect in trench power MOSFETs

It was demonstrated that heavy ions can induce large current-voltage （I-V） characteristics shift in commercial trench power MOSFETs, named single event microdose effect （SE-microdose effect）. A model is pre- sented to describe this effect. This model calculates the charge deposition by a single heavy ion hitting oxide and the subsequent charge transport under an electric field. Holes deposited at the SiO2/Si interface by a Xe ion are calculated by using this model. The calculated results were then used in Sentaurus TCAD software to simulate a trench power MOSFET＇s I-V curve shift after a Xe ion has hit it. The simulation results are consistent with the related experiment＇s data. In the end, several factors which affect the SE-microdose effect in trench power MOSFETs are investigated by using this model.

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor （MOSFET） drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.

Simulation of the sensitive region to SEGR in power MOSFETs

Single event gate rupture（SEGR） is a very important failure mode for power MOSFETs when used in aerospace applications,and the cell regions are widely considered to be the most sensitive to SEGR.However, experimental results show that SEGR can also happen in the gate bus regions.In this paper,we used simulation tools to estimate three structures in power MOSFETs,and found that if certain conditions are met,areas other than cell regions can become sensitive to SEGR.Finally,some proposals are given as to how to reduce SEGR in different regions.

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.

MUIS多脉冲雪崩应力下的器件退化特性

阐述Power MOSFET在多脉冲雪崩应力下的器件电参数退化和退化机制,提出了在半导体工艺制程中改善/延缓MUIS器件退化的方法,对国内集成电路尤其是汽车电子的应用具有参考意义。

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.

Above 700 V superjunction MOSFETs fabricated by deep trench etching and epitaxial growth

Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth,based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited.The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation.The dynamic characteristics, especially reverse diode characteristics,are equivalent or even superior to foreign counterparts.

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region.At OFF state,the low-k dielectric trench（LDT） can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time,the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally,ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics,such as low gateto -drain charge density（〈 0.6 nC/mm^2） and a robust safe operating area（0-84 V）.

The investigation of the zero temperature coefficient point of power MOSFET

The paper investigates the zero temperature coefficient（ZTC） point of power MOSFET,based on the output characteristic of power MOSFET,the temperature coefficient of threshold voltage and the carrier mobility.It is found that the gate voltage has a big effect on the ZTC point.The result indicates that there are three types of temperature coefficient under different gate voltage.When the gate voltage is near the threshold voltage,both the linear region and saturation region shows a large positive temperature coefficient.With the increase of gate voltage,the temperature coefficient of the linear region changes from positive to negative,when the saturation region still remains positive,giving rise to the ZTC point.When the gate voltage is high enough,the negative temperature coefficient is present on both the linear and saturation region,resulting in no ZTC point.According to the experimental result,the change of ZTC point as a function of temperature is larger when the gate voltage is higher.The carrier mobility is also discussed,displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.

Power MOSFET UIS性能改善的研究

分析UIS失效的发生机理,提出了改善UIS性能的三个方面,避免产生极端电场强度、避免缺陷产生电流聚集效应、合适的沟槽深度保证charge balance电荷平衡。并且能够紧扣实验,通过实验结果来详细论证这三个观点。提出在半导体工艺制程和集成电路器件设计过程中改善UIS能力与一致性的方法。

Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs

This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around（GAA） MOSFETs.The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs,namely drain current（/d）,transconductance to drain current ratio（g_m/I_d）,I_（on）/I_（off）,the cut-off frequency（f_T） and the maximum frequency of oscillation（/max） are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator,ATLAS^（TM）.It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics（g_m/I_d,f_T and /max） compared to the nanowire-based gate-all-around GAA MOSFETs.The silicon-nanotube MOSFET shows an improvement of ~2.5 and 3 times in the case of f_T and /max values respectively compared with the nanowire-based gate-all-around（GAA） MOSFET.

Equivalent properties of single event burnout induced by different sources

The experimental results of single event burnout induced by heavy ions and 252Cf fission fragments in power MOSFET devices have been investigated. It is concluded that the characteristics of single event burnout induced by 252Cf fission fragments is consistent to that in heavy ions. The power MOSFET in the ＂turn-off＂ state is more susceptible to single event burnout than it is in the ＂turn-on＂ state. The thresholds of the drain-source voltage for single event burnout induced by 173 MeV bromine ions and ^252Cf fission fragments are close to each other, and the burnout cross section is sensitive to variation of the drain-source voltage above the threshold of single event burnout. In addition, the current waveforms of single event burnouts induced by different sources are similar. Different power MOSFET devices may have different probabilities for the occurrence of single event burnout.

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET （TPMOS） structure based on VD- MOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only im- proves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.