In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabric...In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabricated using the gallium arsenide(GaAs)integrated passive device(IPD)process,is proposed for 5G massive multiple-input multiple-output(MIMO)application.An inverted DPA structure with a low-Q output network is proposed to achieve better bandwidth performance,and a single-driver architecture is adopted for a chip with high gain and small area.The proposed DPA has a bandwidth of 4.4-5.0 GHz that can achieve a saturation of more than 45.0 dBm.The gain compression from 37 dBm to saturation power is less than 4 dB,and the average power-added efficiency(PAE)is 36.3%with an 8.5 dB peak-to-average power ratio(PAPR)in 4.5-5.0 GHz.The measured adjacent channel power ratio(ACPR)is better than50 dBc after digital predistortion(DPD),exhibiting satisfactory linearity.展开更多
In this paper,a simple adaptive power dividing function for the design of a dual-input Doherty power amplifier(DPA)is presented.In the presented approaches,the signal separation function(SSF)at different frequency poi...In this paper,a simple adaptive power dividing function for the design of a dual-input Doherty power amplifier(DPA)is presented.In the presented approaches,the signal separation function(SSF)at different frequency points can be characterized by a polynomial.And in the practical test,the coefficients of SSF can be determined by measuring a small number of data points of input power.Same as other dualinput DPAs,the proposed approach can also achieve high output power and back-off efficiency in a broadband operation band by adjusting the power distribution ratio flexibly.Finally,a 1.5-2.5 GHz highefficiency dual-input Doherty power amplifier is implemented according to this approach.The test results show that the peak power is 48.6-49.7d Bm,and the 6-d B back-off efficiency is 51.0-67.0%,and the saturation efficiency is 52.4-74.6%.The digital predistortion correction is carried out at the frequency points of 1.8/2.1GHz,and the adjacent channel power ratio is lower than-54.5d Bc.Simulation and experiment results can verify the effectiveness and correctness of the proposed method.展开更多
The new 1 kW power module for ADS project needs the optimization of cooling design including water flow and tunnel layout, and the water flow of three tons per hour was chosen to be a goal for a 20 kW power source.Acc...The new 1 kW power module for ADS project needs the optimization of cooling design including water flow and tunnel layout, and the water flow of three tons per hour was chosen to be a goal for a 20 kW power source.According to analysis from the insertion and integrated loss, about 24 modules were integrated into the rated power. Thus, every module has a cooling flow of 2.1 L/min for RF heat load and power supply loss, which is very hard to achieve if no special consideration and techniques. A new thermal simulation method was introduced for thermal analysis of cooling plate through CST multi-physics suite,especially for temperature of power LDMOS transistor.Some specific measures carried out for the higher heat transfer were also presented in this paper.展开更多
Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modu...Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.展开更多
Switch electro-hydraulic proportional amplifier（PA） widely employs single switch modulation power driving（SSMPD） or reverse discharging power driving（RDPD） at present. SSMPD has slow dynamic response, and can＇t...Switch electro-hydraulic proportional amplifier（PA） widely employs single switch modulation power driving（SSMPD） or reverse discharging power driving（RDPD） at present. SSMPD has slow dynamic response, and can＇t adjust independently the dither signal＇s amplitude and frequency; RDPD accelerates the current decay; consequently, it increases current ripple and power loss. For the purpose of solving the above mentioned problem, the tri-state modulation power driving（TSMPD） scheme was proposed for improving the performance of power driving. Detailedly, the hardware circuit for the tri-state modulation power driving is designed; the tri-state modulation algorithm is realized by digital signal processor（DSP）. The tri-state modulation power driving is investigated by experiments, comparetive experiments among the single switch modulation power driving（SSMPD）, reverse discharging power driving（RDPD）, and the TSMPD are implemented, and the experimental results demonstrate that the linearity error of TSMDP meets the requirement of PA; the current response of TSMSP is the best; the amplitude of ripple current of the TSMPD can be reduced without increasing frequency of PWM, in addition, dither signal amplitude and frequency can be adjusted independently for each other. It is very meaningful to guide the development of high performance proportional amplifier for high frequency response proportional solenoid.展开更多
For high-voltage and high-power Gallium Nitride(GaN)power amplifiers,a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time,the high-side bootstrap drive ...For high-voltage and high-power Gallium Nitride(GaN)power amplifiers,a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time,the high-side bootstrap drive circuit with an auxiliary discharge switch is proposed.The effect of the parasitics is analyzed based on calculation and the parallel bonding is proposed.The storage capacitance of power supply is calculated quantitatively to provide large pulse current.To ensure safe operation of the power amplifier,the circuit topology with the dead-time control and sequential control is proposed.Finally,a prototype is built to verify the drain modulation circuit design.The experiments prove that the rise time and fall time of the output pulse signal are both less than 100 ns.展开更多
This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a h...This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a high 37 dB output power dynamic range with good average power adding efficiency. The measurement results show that the PA achieves a high power gain of 23 dBm and power added efficiency (PAE) by 38%. The circuit was post layout simulated in a standard 0.18 μm CMOS technology.展开更多
This paper proposes a new two-branch amplification architecture that combines baseband signal decomposition with RF front-end optimization. In the proposed architecture, the filtered modulated signals are separated in...This paper proposes a new two-branch amplification architecture that combines baseband signal decomposition with RF front-end optimization. In the proposed architecture, the filtered modulated signals are separated into two components that are then amplified independently and combined to regenerate an amplified version of the original signal. A branch with an efficient amplifier transmits a low-varying envelope signal that contains the main part of the information. Another branch amplifies the residual portion of the signal. The baseband decomposition and parameters of the RF part are optimized to find the configuration that gives the best power efficiency and linearity. For M-ary quadrature amplitude modulation （M-QAM） signals, this technique is limited in terms of power efficiency. However, for filtered continuous phase modulation （CPM） signals, especially for minimum shift keying （MSK） and Gaussian MSK （GMSK） signals, high power efficiency can be achieved with no significant impact on the overall linearity. The results show that this technique gives better performance than the single-ended ctass-B amplifier.展开更多
A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-...A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.展开更多
In this paper,a portable 2.42 GHz transmitter for wireless communication systems,with 8dBm output power and small size is proposed.Several novel features exist in this transmitter.First,power consumption and output ar...In this paper,a portable 2.42 GHz transmitter for wireless communication systems,with 8dBm output power and small size is proposed.Several novel features exist in this transmitter.First,power consumption and output are balanced by introducing a differential oscillator with input signal controlled biasing,which acts as both a carrier generator and an OOK modulator.Then,power consumption of the transmitter is reduced by the OOK modulated signal via switching the oscillator and the power amplifier at the same time.Furthermore,the area size is also reduced by a class-AB power amplifier,which uses the PCB antenna as the resonance inductance.With these features,the total chip area is reduced to 670μm×740μm(In a 0.18μm CMOS process).展开更多
基金supported in part by the National Key Research and Development Program of China(2021YFA0716601)the National Science Fund(62225111).
文摘In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabricated using the gallium arsenide(GaAs)integrated passive device(IPD)process,is proposed for 5G massive multiple-input multiple-output(MIMO)application.An inverted DPA structure with a low-Q output network is proposed to achieve better bandwidth performance,and a single-driver architecture is adopted for a chip with high gain and small area.The proposed DPA has a bandwidth of 4.4-5.0 GHz that can achieve a saturation of more than 45.0 dBm.The gain compression from 37 dBm to saturation power is less than 4 dB,and the average power-added efficiency(PAE)is 36.3%with an 8.5 dB peak-to-average power ratio(PAPR)in 4.5-5.0 GHz.The measured adjacent channel power ratio(ACPR)is better than50 dBc after digital predistortion(DPD),exhibiting satisfactory linearity.
基金supported by National Natural Science Foundation of China(No.62001061)。
文摘In this paper,a simple adaptive power dividing function for the design of a dual-input Doherty power amplifier(DPA)is presented.In the presented approaches,the signal separation function(SSF)at different frequency points can be characterized by a polynomial.And in the practical test,the coefficients of SSF can be determined by measuring a small number of data points of input power.Same as other dualinput DPAs,the proposed approach can also achieve high output power and back-off efficiency in a broadband operation band by adjusting the power distribution ratio flexibly.Finally,a 1.5-2.5 GHz highefficiency dual-input Doherty power amplifier is implemented according to this approach.The test results show that the peak power is 48.6-49.7d Bm,and the 6-d B back-off efficiency is 51.0-67.0%,and the saturation efficiency is 52.4-74.6%.The digital predistortion correction is carried out at the frequency points of 1.8/2.1GHz,and the adjacent channel power ratio is lower than-54.5d Bc.Simulation and experiment results can verify the effectiveness and correctness of the proposed method.
基金supported by the ‘‘strategic priority research program’’ of the Chinese Academy of Sciences(No.XDA030205)
文摘The new 1 kW power module for ADS project needs the optimization of cooling design including water flow and tunnel layout, and the water flow of three tons per hour was chosen to be a goal for a 20 kW power source.According to analysis from the insertion and integrated loss, about 24 modules were integrated into the rated power. Thus, every module has a cooling flow of 2.1 L/min for RF heat load and power supply loss, which is very hard to achieve if no special consideration and techniques. A new thermal simulation method was introduced for thermal analysis of cooling plate through CST multi-physics suite,especially for temperature of power LDMOS transistor.Some specific measures carried out for the higher heat transfer were also presented in this paper.
文摘Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.
基金supported by National Basic Research and Development Program of China (973 Program, Grant No. 2007CB714000)National Natural Science Foundation of China (Grant No. 50875233)
文摘Switch electro-hydraulic proportional amplifier（PA） widely employs single switch modulation power driving（SSMPD） or reverse discharging power driving（RDPD） at present. SSMPD has slow dynamic response, and can＇t adjust independently the dither signal＇s amplitude and frequency; RDPD accelerates the current decay; consequently, it increases current ripple and power loss. For the purpose of solving the above mentioned problem, the tri-state modulation power driving（TSMPD） scheme was proposed for improving the performance of power driving. Detailedly, the hardware circuit for the tri-state modulation power driving is designed; the tri-state modulation algorithm is realized by digital signal processor（DSP）. The tri-state modulation power driving is investigated by experiments, comparetive experiments among the single switch modulation power driving（SSMPD）, reverse discharging power driving（RDPD）, and the TSMPD are implemented, and the experimental results demonstrate that the linearity error of TSMDP meets the requirement of PA; the current response of TSMSP is the best; the amplitude of ripple current of the TSMPD can be reduced without increasing frequency of PWM, in addition, dither signal amplitude and frequency can be adjusted independently for each other. It is very meaningful to guide the development of high performance proportional amplifier for high frequency response proportional solenoid.
基金supported by the Pri⁃mary Research&Development Plan of Jiangsu Province(Nos.BE2022070,BE2022070-2).
文摘For high-voltage and high-power Gallium Nitride(GaN)power amplifiers,a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time,the high-side bootstrap drive circuit with an auxiliary discharge switch is proposed.The effect of the parasitics is analyzed based on calculation and the parallel bonding is proposed.The storage capacitance of power supply is calculated quantitatively to provide large pulse current.To ensure safe operation of the power amplifier,the circuit topology with the dead-time control and sequential control is proposed.Finally,a prototype is built to verify the drain modulation circuit design.The experiments prove that the rise time and fall time of the output pulse signal are both less than 100 ns.
文摘This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a high 37 dB output power dynamic range with good average power adding efficiency. The measurement results show that the PA achieves a high power gain of 23 dBm and power added efficiency (PAE) by 38%. The circuit was post layout simulated in a standard 0.18 μm CMOS technology.
文摘This paper proposes a new two-branch amplification architecture that combines baseband signal decomposition with RF front-end optimization. In the proposed architecture, the filtered modulated signals are separated into two components that are then amplified independently and combined to regenerate an amplified version of the original signal. A branch with an efficient amplifier transmits a low-varying envelope signal that contains the main part of the information. Another branch amplifies the residual portion of the signal. The baseband decomposition and parameters of the RF part are optimized to find the configuration that gives the best power efficiency and linearity. For M-ary quadrature amplitude modulation （M-QAM） signals, this technique is limited in terms of power efficiency. However, for filtered continuous phase modulation （CPM） signals, especially for minimum shift keying （MSK） and Gaussian MSK （GMSK） signals, high power efficiency can be achieved with no significant impact on the overall linearity. The results show that this technique gives better performance than the single-ended ctass-B amplifier.
基金Project Supported by the Important National Science & Technology Specific Projects of China(No.2009ZXO1O31-003-002)the State Key Laboratory Project of China(No.11MS002)
文摘A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.
基金Supported by the National Natural Science Foundation of China(No.61072010)
文摘In this paper,a portable 2.42 GHz transmitter for wireless communication systems,with 8dBm output power and small size is proposed.Several novel features exist in this transmitter.First,power consumption and output are balanced by introducing a differential oscillator with input signal controlled biasing,which acts as both a carrier generator and an OOK modulator.Then,power consumption of the transmitter is reduced by the OOK modulated signal via switching the oscillator and the power amplifier at the same time.Furthermore,the area size is also reduced by a class-AB power amplifier,which uses the PCB antenna as the resonance inductance.With these features,the total chip area is reduced to 670μm×740μm(In a 0.18μm CMOS process).
