A gate level maximum power supply noise （PSN） model is defined that captures both IR drop and di/dt noise effects. Experimental results show that this model improves PSN estimation by 5.3% on average and reduces com...A gate level maximum power supply noise （PSN） model is defined that captures both IR drop and di/dt noise effects. Experimental results show that this model improves PSN estimation by 5.3% on average and reduces computation time by 10.7% compared with previous methods. Furthermore,a primary input critical factor model that captures the extent of primary inputs＇ PSN contribution is formulated. Based on these models,a novel niche genetic algorithm is proposed to estimate PSN more effectively. Compared with general genetic algorithms, this novel method can achieve up to 19.0% improvement on PSN estimation with a much higher convergence speed.展开更多
Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up ...Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise （PSN） interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network （PDN） solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.展开更多
In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic contro...In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic controller (FLC). This results in automatically corrected output impedance for different cables with terminations. Also, the line driver output impedance and gain become insensitive to process and line variations. As an example, a line driver for ADSL application has been designed. The circuit operates from a 3.3 v in a 0.35 um standard CMOS technology. The power consumption of FLC is about 1 mW. The circuit dissipates 106 mW and exhibits a -62 dB THD for a 3.2-Vpp signal at 5 MHz across a 75 ohms Load. It has a relatively high -3 dB bandwidth (240 MHz) with good phase margin of about 67 degrees in a 10 pF load capacitor.展开更多
文摘A gate level maximum power supply noise （PSN） model is defined that captures both IR drop and di/dt noise effects. Experimental results show that this model improves PSN estimation by 5.3% on average and reduces computation time by 10.7% compared with previous methods. Furthermore,a primary input critical factor model that captures the extent of primary inputs＇ PSN contribution is formulated. Based on these models,a novel niche genetic algorithm is proposed to estimate PSN more effectively. Compared with general genetic algorithms, this novel method can achieve up to 19.0% improvement on PSN estimation with a much higher convergence speed.
基金This work was supported by the National Natural Science Foundation of China under Grant Nos. 61401008 and 61602022, and the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, under Grant No. CARCH201602.
文摘Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise （PSN） interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network （PDN） solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.
文摘In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic controller (FLC). This results in automatically corrected output impedance for different cables with terminations. Also, the line driver output impedance and gain become insensitive to process and line variations. As an example, a line driver for ADSL application has been designed. The circuit operates from a 3.3 v in a 0.35 um standard CMOS technology. The power consumption of FLC is about 1 mW. The circuit dissipates 106 mW and exhibits a -62 dB THD for a 3.2-Vpp signal at 5 MHz across a 75 ohms Load. It has a relatively high -3 dB bandwidth (240 MHz) with good phase margin of about 67 degrees in a 10 pF load capacitor.
