Sub-1V CMOS Voltage Reference Based on Weighted V_(gs)

We propose a voltage reference based on the weighted difference between the gate-source voltages of an nMOS and a pMOS operating in their saturation regions. No diodes or parasitic bipolar transistors are used, The circuit is simulated and fabricated with SMIC 0.18μm mixed-signal technology,and our measurements demonstrate that its temperature coefficient is 44ppm/℃ and its PSRR is - 46dB, It works well when Vdd is above 650mV. The active area of the circuit is about 0.05mm^2.

IC Implementation of a Programmable CMOS Voltage Reference

A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV.

A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.

宽负载范围的高PSRR线性电源研究

研究分析了线性稳压电源中电源对稳压输出的噪声影响途径,提出了一种与负载无关的高PSRR线性稳压器电路。为减小电源噪声对LDO模块电路的影响,基于带隙基准源内部的自建电压实现高压和低噪声隔离,抑制了传统结构带来的功耗、面积和噪声问题。基于0.18μm、40 V高压BCD工艺进行了具体电路设计与芯片实现,经过全面验证,在电源电压为4.5 V到32 V,输出电容为2.2μF,最大负载电流为200 mA的条件下,LDO可提供3.3 V的稳定电压源,空载时PSRR可达到80.5 dB,负载为200 mA下PSRR仍然高达80.23 dB;变化率仅为0.001 dB/mA,实现了与负载无关的高PSRR线性稳压器设计。

An extremely low power voltage reference with high PSRR for power-aware ASICs

An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio （PSRR） and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed circuit is implemented;the active die area is 0.17×0.20 mm;. Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from -40 to 150℃,the power supply rejection ratio is -98.2 dB,the line regulation is 0.3 mV/V,and the power consumption is only 0.38 mW.The proposed bandgap voltage reference has good characteristics such as small area,low power consumption, good temperature stability,high power supply rejection ratio,as well as low line regulation.This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog,digital and mixed systems.

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio （PSRR） high-order temperature-compensated subthreshold metal-oxidesemiconductor （MOS） bandgap reference （BGR） is proposed in Semiconductor Manufacturing International Corporation （SMIC） 0.13 gm complementary MOS （CMOS） process. By adopting subthreshold MOS field-effect transistors （MOSFETs） and the piecewise-curvature temperature-compensated technique, the output reference voltage＇s temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient （TC） of the subthreshold MOS BGR is 1.38× 10^-6/℃ when temperature is changed from -40 ℃ to 125 ℃ with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of - 104.54 dB, - 104.54 dB,- 104.5 dB, - 101.82 dB and - 79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.

A 0.19 ppm/°C bandgap reference circuit with high-PSRR

A high-order curvature-compensated CMOS bandgap reference（BGR） topology with a low temperature coefficient（TC） over a wide temperature range and a high power supply reject ratio（PSRR） is presented.High-order correction is realized by incorporating a nonlinear current INL, which is generated by ？V_（GS） across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of0.19 ppm/°C over the temperature range of 165 °C（-40 to 125 °C）, PSRR of-123 d B @ DC and-56 d B @ 100 k Hz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

This paper proposes a novel high-power supply rejection ratio（high-PSRR） high-order curvature-compensated CMOS bandgap voltage reference（BGR） in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvaturecorrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T^（1.5） current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42x10^（-6）′ /℃ from - 55 ℃ to 125 ℃ with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of - 123.51 dB, - 123.52 dB, - 88.5 dB and - 50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.

A capacitor-free high PSR CMOS low dropout voltage regulator

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC （Shanghai, China）. Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO＇s active chip-area is only smaller than 0.02 mm2.