In-package P/G planes analysis and optimization based on transmission matrix method

Power integrity (PI) has become a limiting factor for the chip's overall performance, and how to place in-package decoupling capacitors to improve a chip's PI performance has become a hot issue. In this paper, we propose an improved trans- mission matrix method (TMM) for fast decoupling capacitance allocation. An irregular grid partition mechanism is proposed, which helps speed up the impedance computation and complies better with the irregular power/ground (P/G) plane or planes with many vias and decoupling capacitors. Furthermore, we also ameliorate the computation procedure of the impedance matrix whenever decoupling capacitors are inserted or removed at specific ports. With the fast computation of impedance change, in-package decoupling capacitor allocation is done with an efficient change based method in the frequency domain. Experimental results show that our approach can gain about 5× speedup compared with a general TMM, and is efficient in restraining the noise on the P/G plane.

基于几何多网格的RLC电源网络的瞬态模拟

提出了一种高效的、针对VLSI中Mesh拓扑结构的RLC电源线地线网络的时域分析算法该算法首次利用一种基于启发式原则的电路模型的简化方法来缩小电路网络的规模,扩展了原有的几何多网格方法来模拟求解以RLC元件建模的电源线网络实验数据表明,对于一些规模较大的电路实例,在一个较小的误差损失下,该算法能大幅缩小电路的求解规模,求解速度比SPICE快两个数量级以上, 比原有的几何多网格方法也有大幅的提高如在Sun工作站上,当误差控制在1 5%时。