Biodegradable and flexible i-carrageenan based RRAM with ultralow power consumption

Transient memories,which can physically disappear without leaving traceable remains over a period of normal operation,are attracting increasing attention for potential applications in the fields of data security and green electronics.Resistive random access memory(RRAM)is a promising candidate for next-generation memory.In this context,biocompatible l-carrageenan(l-car),extracted from natural seaweed,is introduced for the fabrication of RRAM devices(Ag/l-car/Pt).Taking advantage of the complexation processes between the functional groups(C–O–C,C–O–H,et al.)and Ag metal ions,a lower migration barrier of Ag ions and a high-speed switching(22.2 ns for SET operation/26 ns for RESET operation)were achieved,resulting in an ultralow power consumption of 56 fJ.And the prepared Ag/l-car/Pt RRAM devices also revealed the capacities of multilevel storage and flexibility.In addition,thanks to the hydrophilic groups of l-car molecule,the RRAM devices can be rapidly dissolved in deionized(DI)water within 13 minutes,showing excellent transient characteristics.This work demonstrates that l-car based RRAM devices have great potential for applications in secure storage applications,flexible electronics and transient electronics.

A Hybrid Integrated and Low-Cost Multi-Chip Broadband Doherty Power Amplifier Module for 5G Massive MIMO Application

In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabricated using the gallium arsenide(GaAs)integrated passive device(IPD)process,is proposed for 5G massive multiple-input multiple-output(MIMO)application.An inverted DPA structure with a low-Q output network is proposed to achieve better bandwidth performance,and a single-driver architecture is adopted for a chip with high gain and small area.The proposed DPA has a bandwidth of 4.4-5.0 GHz that can achieve a saturation of more than 45.0 dBm.The gain compression from 37 dBm to saturation power is less than 4 dB,and the average power-added efficiency(PAE)is 36.3%with an 8.5 dB peak-to-average power ratio(PAPR)in 4.5-5.0 GHz.The measured adjacent channel power ratio(ACPR)is better than50 dBc after digital predistortion(DPD),exhibiting satisfactory linearity.

Low-frequency oscillation of train-network system considering traction power supply mode

The low-frequency oscillation(LFO)has occurred in the train-network system due to the introduction of the power electronics of the trains.The modeling and analyzing method in current researches based on electrified railway unilateral power supply system are not suitable for the LFO analysis in a bilateral power supply system,where the trains are supplied by two traction substations.In this work,based on the single-input and single-output impedance model of China CRH5 trains,the node admittance matrices of the train-network system both in unilateral and bilateral power supply modes are established,including three-phase power grid,traction transformers and traction network.Then the modal analysis is used to study the oscillation modes and propagation characteristics of the unilateral and bilateral power supply systems.Moreover,the influence of the equivalent inductance of the power grid,the length of the transmission line,and the length of the traction network are analyzed on the critical oscillation mode of the bilateral power supply system.Finally,the theoretical analysis results are verified by the time-domain simulation model in MATLAB/Simulink.

Increasing the Efficiency and Level of Environmental Safety of Pro-Environmental City Heat Supply Technologies by Low Power Nuclear Plants

In connection with the current prospect of decarbonization of coal energy through the use of small nuclear power plants (SNPPs) at existing TPPs as heat sources for heat supply to municipal heating networks, there is a technological need to improve heat supply schemes to increase their environmental friendliness and efficiency. The paper proves the feasibility of using the heat-feeding mode of ASHPs for urban heat supply by heating the network water with steam taken from the turbine. The ratio of electric and thermal power of a “nuclear” combined heat and power plant is given. The advantage of using a heat pump, which provides twice as much electrical power with the same heat output, is established. Taking into account that heat in these modes is supplied with different potential, the energy efficiency was used to compare these options. To increase the heat supply capacity, a scheme with the use of a high-pressure heater in the backpressure mode and with the heating of network water with hot steam was proposed. Heat supply from ASHPs is efficient and environmentally friendly even in the case of significant remoteness of heat consumers.

Enhancing Renewable Energy Integration:A Gaussian-Bare-Bones Levy Cheetah Optimization Approach to Optimal Power Flow in Electrical Networks

In the contemporary era,the global expansion of electrical grids is propelled by various renewable energy sources(RESs).Efficient integration of stochastic RESs and optimal power flow(OPF)management are critical for network optimization.This study introduces an innovative solution,the Gaussian Bare-Bones Levy Cheetah Optimizer(GBBLCO),addressing OPF challenges in power generation systems with stochastic RESs.The primary objective is to minimize the total operating costs of RESs,considering four functions:overall operating costs,voltage deviation management,emissions reduction,voltage stability index(VSI)and power loss mitigation.Additionally,a carbon tax is included in the objective function to reduce carbon emissions.Thorough scrutiny,using modified IEEE 30-bus and IEEE 118-bus systems,validates GBBLCO’s superior performance in achieving optimal solutions.Simulation results demonstrate GBBLCO’s efficacy in six optimization scenarios:total cost with valve point effects,total cost with emission and carbon tax,total cost with prohibited operating zones,active power loss optimization,voltage deviation optimization and enhancing voltage stability index(VSI).GBBLCO outperforms conventional techniques in each scenario,showcasing rapid convergence and superior solution quality.Notably,GBBLCO navigates complexities introduced by valve point effects,adapts to environmental constraints,optimizes costs while considering prohibited operating zones,minimizes active power losses,and optimizes voltage deviation by enhancing the voltage stability index(VSI)effectively.This research significantly contributes to advancing OPF,emphasizing GBBLCO’s improved global search capabilities and ability to address challenges related to local minima.GBBLCO emerges as a versatile and robust optimization tool for diverse challenges in power systems,offering a promising solution for the evolving needs of renewable energy-integrated power grids.

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

This work details the development of a broad-spectrum LNA (Low Noise Amplifier) circuit using a 65 nm CMOS technology. The design incorporates an inductive degeneracy circuit, employing a theoretical approach to enhance gain, minimize noise levels, and uphold low power consumption. The progression includes a shift to a cascode structure to further refine LNA parameters. Ultimately, with a 1.8 V bias, the achieved performance showcases a gain-to-noise figure ratio of 16 dB/0.5 dB, an IIP3 linearity at 5.1 dBm, and a power consumption of 3 mW. This architecture is adept at operating across a wide frequency band spanning from 0.5 GHz to 6 GHz, rendering it applicable in diverse RF scenarios.

Optimizing Power Flow in Northern Cameroon’s Interconnected Grid: Challenges and Solutions

This paper presents an analysis of the power flow within the Northern Interconnected Grid of Cameroon. The Newton-Raphson method has been performed, known for its accuracy, under MATLAB software, to model and solve complex power flow equations. This study simulates a series of outage scenarios to evaluate the responsiveness of the grid. The results obtained underline the crucial importance of reactive power management and highlight the urgent need to consolidate the grid infrastructure of North Cameroon. To increase grid resilience and stability, the paper recommends the strategic integration of renewables and the development of interconnections with other power grids. These measures are presented as viable solutions to meet current and future energy distribution challenges, ensuring a reliable and sustainable power supply for Cameroon.

Mathematical Modeling and Control Algorithm Development for Bidirectional Power Flow in CCS-CNT System

As the demand for more efficient and adaptable power distribution systems intensifies, especially in rural areas, innovative solutions like the Capacitor-Coupled Substation with a Controllable Network Transformer (CCS-CNT) are becoming increasingly critical. Traditional power distribution networks, often limited by unidirectional flow capabilities and inflexibility, struggle to meet the complex demands of modern energy systems. The CCS-CNT system offers a transformative approach by enabling bidirectional power flow between high-voltage transmission lines and local distribution networks, a feature that is essential for integrating renewable energy sources and ensuring reliable electrification in underserved regions. This paper presents a detailed mathematical representation of power flow within the CCS-CNT system, emphasizing the control of both active and reactive power through the adjustment of voltage levels and phase angles. A control algorithm is developed to dynamically manage power flow, ensuring optimal performance by minimizing losses and maintaining voltage stability across the network. The proposed CCS-CNT system demonstrates significant potential in enhancing the efficiency and reliability of power distribution, making it particularly suited for rural electrification and other applications where traditional methods fall short. The findings underscore the system's capability to adapt to varying operational conditions, offering a robust solution for modern power distribution challenges.

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.

Low Power Polarity Conversion Based on the Whole Annealing Genetic Algorithm

For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decomposition algorithm of a multi-input XOR/AND gate,and the multiple segment algorithm of polarity conversion,this paper successfully applies the whole annealing genetic algorithm （WAGA） to find the best polarity of an RM circuit. Through testing eight large-scale circuits from the Microelectronics Center North Carolina （MCNC） Benchmark, the SYNOPSYS synthesis results show that the RM circuits corresponding to the best polarity found using the proposed algorithm attain average power,area,and max delay savings of 77.2% ,62.4% ,and 9.2% respectively,compared with those under polarity 0.

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.

Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.

Low Power Design Orienting 384×288 Snapshot Infrared Readout Integrated Circuits

This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.

Implementation and noise optimization of a 433 MHz low power CMOS LNA

A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

A low-phase-noise and low-power crystal oscillator for RF tuner

A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.

Low-Power CMOS IC for Function Electrical Stimulation of Nerves

A low-power IC for function electrical stimulation （FES） of nerves is designed for an implantable system and fabricated in CSMC＇s 0.6μm CMOS technology. The IC can be used for stimulating animals＇ spinal nerve bundles and other nerves connected with a cuff type electrode. It consists of a pre-amplifier,a main amplifier,and an output stage. According to the neural signal spectrum,the bandwidth of the FES signal generator circuit is defined from 1Hz to 400kHz. The gain of the circuit is about 66dB with an output impedance of 900. The 1C can function under a single supply voltage of 3-5V. A rail-to-rail output stage helps to use the coupled power efficiently. The measured time domain performance shows that the bandwidth and the gain of the IC agree with the design. The power consumption is lower than 6mW.

A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

ICU患者置入Power PICC导管特殊异位原因分析

目的:探讨ICU患者置入Power PICC导管后头端反折向上至同侧和对侧锁骨下静脉、头臂静脉等特殊异位的相关因素。方法:回顾性分析2021年9月至2022年9月某三甲医院ICU 520例PICC置管患者,通过胸部X线确定PICC导管头端反折向上至对侧和同侧锁骨下静脉、头臂静脉的患者,分析其特殊异位发生因素。结果:胸部X线结果显示25例患者PICC管头端反折向上异位至对侧和同侧锁骨下静脉、头臂静脉或颈内静脉,异位发生率4.8%,不同静脉置管反折异位发生率相比差异无统计学意义,P>0.05。结论:ICU患者PICC置入发生导管头端反折向上至同侧和对侧锁骨下静脉、头臂静脉等特殊异位的发生因素较多,包括同时留置CVC或血透管、正在滴注或泵入多种药物、PICC管头端异位的隐匿性、导管材质、自身疾病及机械通气等危险因素。

A New Structure for a CMOS Audio Power AMP with Extremely Low THD and Low Power Consumption

A new system-corrected CMOS audio power AMP is presented. Consisting of four single-end OPAs,this structure is a pseudo-differential system. Compared to conventional CMOS power AMPs, it has the merits of low power consumption, extremely low THD,easy compensation, and good driving capability. With 1st silicon 0.25μm 1P4M CMOS technology and a 3V power supply,the output range can be 4Vpp when driving an 8Ω‖ 300pF load, while its power dissipation is less than 3mW. The THD is better than 0. 003% at 1kHz. A new over-current protection circuit, which can effectively protect the power output circuits on the chip, is also demonstrated.

Equivalent Method of Integrated Power Generation System of Wind, Photovoltaic and Energy Storage in Power Flow Calculation and Transient Simulation

针对工程实际开展风光储联合发电系统在潮流计算和机电暂态仿真中的等值方法研究，旨在为大容量风光储联合发电系统的并网仿真分析奠定基础。将潮流计算的等值分为单元机组和集电系统2部分来研究。单元机组等值采用根据不同控制模式选取不同节点类型的方法，针对集电系统等值提出基于损耗不变原则的方法。等值模型和详细模型的算例结果表明，潮流计算等值方法具有较好的精度。在机电暂态仿真动态等值中，基于实际工程计算的最严重工况分析原则，提出运行在满出力点的单机“倍乘”等值模型，为工程计算中的风光储联合发电系统动态等值提供了一种解决方案。