无线传感器网络中PEGASIS协议的研究与改进

针对PEGASIS协议中通信时延长、节点与节点之间存在长链、网络维护代价大的缺点,该论文在分析和仿真PEGASIS协议的基础上提出一种改进协议PEGASIS-I(PEGASIS-Improved)。该协议将监测区域看成是以基站为中心的圆形区域,基站生成参数θ并将圆形区域分成2π/θ个子区域,子区域内节点与节点形成通信路由树,数据先从树叶传输至树根,再由树根发送至基站。MATLAB仿真表明:与PEGASIS协议相比PEGASIS-I协议有效降低了数据传输延迟58%、避免了长链、延长了网络生存时间198%。

A Minimum-energy Path-preserving Topology Control Algorithm for Wireless Sensor Networks

The topology control strategies of wireless sensor networks are very important for reducing the energy consumption of sensor nodes and prolonging the life-span of networks. In this paper, we put forward a minimum-energy path-preserving topology control （MPTC） algorithm based on a concept of none k-redundant edges. MPTC not only resolves the problem of excessive energy consumption because of the unclosed region in small minimum-energy communication network （SMECN）, but also preserves at least one minimum-energy path between every pair of nodes in a wireless sensor network. We also propose an energy-efficient reconfiguration protocol that maintains the minimum-energy path property in the case where the network topology changes dynamically. Finally, we demonstrate the performance improvements of our algorithm through simulation.

A Novel Low-Complexity Low-Latency Power Efficient Collision Detection Algorithm for Wireless Sensor Networks

Collision detection mechanisms in Wireless Sensor Networks (WSNs) have largely been revolving around direct demodulation and decoding of received packets and deciding on a collision based on some form of a frame error detection mechanism, such as a CRC check. The obvious drawback of full detection of a received packet is the need to expend a significant amount of energy and processing complexity in order to fully decode a packet, only to discover the packet is illegible due to a collision. In this paper, we propose a suite of novel, yet simple and power-efficient algorithms to detect a collision without the need for full-decoding of the received packet. Our novel algorithms aim at detecting collision through fast examination of the signal statistics of a short snippet of the received packet via a relatively small number of computations over a small number of received IQ samples. Hence, the proposed algorithms operate directly at the output of the receiver's analog-to-digital converter and eliminate the need to pass the signal through the entire. In addition, we present a complexity and power-saving comparison between our novel algorithms and conventional full-decoding (for select coding schemes) to demonstrate the significant power and complexity saving advantage of our algorithms.

CASA:A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs

The instruction fetch unit （IFU） usually dissipates a considerable portion of total chip power. In traditional IFU architectures, as soon as the fetch address is generated, it needs to be sent to the instruction cache and TLB arrays for instruction fetch. Since limited work can be done by the power-saving logic after the fetch address generation and before the instruction fetch, previous power-saving approaches usually suffer from the unnecessary restrictions from traditional IFU architectures. In this paper, we present CASA, a new power-aware IFU architecture, which effectively reduces the unnecessary restrictions on the power-saving approaches and provides sufficient time and information for the power-saving logic of both instruction cache and TLB. By analyzing, recording, and utilizing the key information of the dynamic instruction flow early in the front-end pipeline, CASA brings the opportunity to maximize the power efficiency and minimize the performance overhead. Compared to the baseline configuration, the leakage and dynamic power of instruction cache is reduced by 89.7% and 64.1% respectively, and the dynamic power of instruction TLB is reduced by 90.2%. Meanwhile the performance degradation in the worst case is only 0.63%. Compared to previous state-of-the-art power-saving approaches, the CASA-based approach saves IFU power more effectively, incurs less performance overhead and achieves better scalability. It is promising that CASA can stimulate further work on architectural solutions to power-efficient IFU designs.

A power-efficient switchable CML driver at 10 Gbps

High static power limits the application of conventional current-mode logic （CML）. This paper presents a power-efficient switchable CML driver, which achieves a significant current saving by 75% compared with con- ventional ones. Implemeuted in the 130 nm CMOS technology process, the proposed CML driver just occupies an area about 0.003 mm2 and provides a robust differential signal of 1600 mV for 10 Gbps optical line terminal （OLT） with a total current of 10 mA. The peak-to-peak jitter is about 4 ps （0.04Tut） and the offset voltage is 347.2 mV @ 1600 mVpp.

Investigation of cost, power, and spectral efficiency in fixed- and flexi-grid networks

With the steady growth of traffic volume in core networks,it is predicted that future optical network communication will be constrained mainly by cost and power consumption.Thus,for Internet sustainability,it will be necessary to ensure cost and power efficiency in optical networks.The aims of this study are(i)to identify the main sources of cost and power consumption in fixed-grid(SLR and MLR)and flexi-grid(OFDM)optical networks,and(ii)to compare techniques for improving cost and power efficiency in SLR/MLR-and OFDM-based networks.To this end,we conducted a comparative analysis of cost and power efficiency for the OFDM-and MLR/SLR-based networks,and considering realistic networks,evaluated the cost and power consumed by different components in the optical layer.Our results show that(i)OFDM-based networks outperform those based on MLR/SLR in terms of both cost and power-efficiency,(ii)the extra equipment cost incurred due to under-utilization of spectrum is reduced by switching to a flexi-grid network,(iii)lower power consumption per bit is obtained when the networking solution ensures a finer bit-rate granularity,and(iv)there exists a power and spectrum minimization trade-off that is network characteristic dependent.