Fast-scale border collision bifurcation in SEPIC power factor pre-regulators

In this paper we report a kind of fast-scale instability occurring in the single-ended primary inductance converter （SEPIC） power factor pre-regulator, which is designed to operate in discontinuous conduction mode. Main results are given by exact cycle-by-cycle computer simulations as well as theoretical analysis. It is found that the instability phenomenon manifests itself as a fast-scale bifurcation at the switching period, which implies the occurrence of border collision bifurcation, or is related to the transition of the regular operating mode of the SEPIC. According to the theoretical analysis and simulation results, the effects of parameters on system stability, and the locations of the bifurcation points are confirmed. Moreover, the effects of such an instability on power factor and switching stress are also discussed. Finally, the occurrence of the asymmetric bifurcation locations is investigated. The results show that this work provides a convenient means of predicting stability boundaries which can facilitate the selection of the practical parameters.

A High-PSRR CMOS Bandgap Reference Without Resistor

A CMOS bandgap reference （BGR） without a resistor,with a high power supply rejection ratio and output be- low 1V is proposed. The circuit is suited for on-chip voltage down converters. The BGR is designed and fabricated using an HUTC 0.18μm CMOS process. The silicon area is only 0. 031mm^2 excluding pads and electrostatic-discharge （ESD） protec- tion circuits. Experimental results show that the PSRR of the proposed BGR at 100Hz and lkHz achieves, respectively, - 70 and 62dB using the pre-regulator. The proposed BGR circuit generates an output voltage of 0. 5582V with a varia- tion of 1.5mV in a temperature range from 0 to 85℃. The deviation of the output voltage is within 2mV when the power supply voltage VDD changes from 2.4 to 4V.

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio （PSRR） high-order temperature-compensated subthreshold metal-oxidesemiconductor （MOS） bandgap reference （BGR） is proposed in Semiconductor Manufacturing International Corporation （SMIC） 0.13 gm complementary MOS （CMOS） process. By adopting subthreshold MOS field-effect transistors （MOSFETs） and the piecewise-curvature temperature-compensated technique, the output reference voltage＇s temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient （TC） of the subthreshold MOS BGR is 1.38× 10^-6/℃ when temperature is changed from -40 ℃ to 125 ℃ with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of - 104.54 dB, - 104.54 dB,- 104.5 dB, - 101.82 dB and - 79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

This paper proposes a novel high-power supply rejection ratio（high-PSRR） high-order curvature-compensated CMOS bandgap voltage reference（BGR） in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvaturecorrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T^（1.5） current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42x10^（-6）′ /℃ from - 55 ℃ to 125 ℃ with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of - 123.51 dB, - 123.52 dB, - 88.5 dB and - 50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.