Design of logic process based low-power 512-bit EEPROM for UHF RFID tag chip

A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.

A Photolithography Process Design for 5 nm Logic Process Flow

With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.

Design of 512-bit logic process-based single poly EEPROM IP

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.

Modeling and Analysis of Data Dependencies in Business Process for Data-Intensive Services

With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependencies, resulting in the inflexibility of the design and implement for the processes. This paper proposes a novel data-aware business process model which is able to describe both explicit control flow and implicit data flow. Data model with dependencies which are formulated by Linear-time Temporal Logic(LTL) is presented, and their satisfiability is validated by an automaton-based model checking algorithm. Data dependencies are fully considered in modeling phase, which helps to improve the efficiency and reliability of programming during developing phase. Finally, a prototype system based on j BPM for data-aware workflow is designed using such model, and has been deployed to Beijing Kingfore heating management system to validate the flexibility, efficacy and convenience of our approach for massive coding and large-scale system management in reality.

Practical Issues Concerning Moment Invariants

In this report several practical issues about moment invariants with application to image classification are concerned. A modified formulation for the approximation of the moments of digital images is suggested. Four computational procedures and their corresponding noise performances are studied in detail.

PRODUCT MODELING AND PROCESS PLANNING WITHIN CONCURRENT ENGINEERING ENVIRONMENT

A prodouct modeling and a process planning that are two essential basses of realizing concurrent engineering are investigated , a logical modeling technique , grammar representation scheme of technology knowledge and architecture of expert system for process planning within con- current engineering environment are proposed. They have been utilized in a real reaserch project.