Proposal for sequential Stern-Gerlach experiment with programmable quantum processors

The historical significance of the Stern–Gerlach(SG)experiment lies in its provision of the initial evidence for space quantization.Over time,its sequential form has evolved into an elegant paradigm that effectively illustrates the fundamental principles of quantum theory.To date,the practical implementation of the sequential SG experiment has not been fully achieved.In this study,we demonstrate the capability of programmable quantum processors to simulate the sequential SG experiment.The specific parametric shallow quantum circuits,which are suitable for the limitations of current noisy quantum hardware,are given to replicate the functionality of SG devices with the ability to perform measurements in different directions.Surprisingly,it has been demonstrated that Wigner’s SG interferometer can be readily implemented in our sequential quantum circuit.With the utilization of the identical circuits,it is also feasible to implement Wheeler’s delayed-choice experiment.We propose the utilization of cross-shaped programmable quantum processors to showcase sequential experiments,and the simulation results demonstrate a strong alignment with theoretical predictions.With the rapid advancement of cloud-based quantum computing,such as BAQIS Quafu,it is our belief that the proposed solution is well-suited for deployment on the cloud,allowing for public accessibility.Our findings not only expand the potential applications of quantum computers,but also contribute to a deeper comprehension of the fundamental principles underlying quantum theory.

Efficient cache replacement framework based on access hotness for spacecraft processors

A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.

Energy Efficient Hyperparameter Tuned Deep Neural Network to Improve Accuracy of Near-Threshold Processor

When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.

Controller Design for Induction and Brushless Motors Using Matlab with Digital Signal Processor (DSP)

The automation process is a very important pillar for Industry 4.0.One of the first steps is the control of motors to improve production efficiency and generate energy savings.In mass production industries,techniques such as digital signal processing(DSP)systems are implemented to control motors.These systems are efficient but very expensive for certain applications.From this arises the need for a controller capable of handling AC and DC motors that improves efficiency and maintains low energy consumption.This project presents the design of an adaptive control system for brushless AC induction and DC motors,which is functional to any type of plant in the industry.The design was possible by implementing Matlab software and tools such as digital signal processor(DSP)and Simulink.Through an extensive investigation of the state of the art,three models needed to represent the control system have been specified.The first model for the AC motor,the second for the DC motor and the third for the DSP control;this is done in this way so that the probability of failure is lower.Subsequently,these models have been programmed in Simulink,integrating the three main models into one.In this way,the design of a controller for use in AC induction motors,specifically squirrel cage and brushless DC motors,has been achieved.The final model represents a response time of 0.25 seconds,which is optimal for this type of application,where response times of 2e-3 to 3 seconds are expected.

DEVELOPMENT OF AN AIRBORNE SAR REAL-TIME DIGITAL IMAGING PROCESSOR

An airborne SAR real-time digital imaging processor is presented, and its realtime digital imaging principle and main technical parameters are analyzed briefly. The system configuration and logical structure are described in detail. Finally the main features of this system and examples of imagery obtained with the system are also presented.

基于双DSP(Digital Signal Processor)结构的有源滤波器检测及控制系统

简要介绍了DigitalSignalProcessor(DSP)的发展及其性能特点 ,详细讨论了一种利用双DSP构成的有源滤波器检测及控制系统的实现和基本结构及算法 .

A VLIW Architecture Stream Cryptographic Processor for Information Security

As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

The history of Cochlear^(TM) Nucleus~ sound processor upgrades:30 years and counting

Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.

一种用于Multi-Processor测量系统的NOC结构的路由节点设计及性能评估

本文提出了一种用于多处理器(Multi-Processor)测量系统的NOC结构的路由节点的微结构,并详细描述了路由节点的各个部分结构及其各自功能。为了说明本文提出的结构的可行性和实用性,本文设计了一套以DSP和FPGA为基础的用于NOC结构仿真的硬件平台,评估了路由节点的资源消耗。最后,本文通过16个路由节点建立了一个基于4×4Mesh拓扑结构的NOC。通过仿真,得到了该网络在不同通信模式下的不同注入率情况下的延时、吞吐率、和面积消耗等性能,并与采用输出缓冲的路由节点进行了比较。同时,针对VOQ(virtual output queue)和输出缓冲大小这两个影响网络性能的重要微结构参数,给出了比较和分析结果。

Performance assessment of a spiral methanol to hydrogen fuel processor for fuel cell applications

A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.

Image processing algorithm acceleration using reconfigurable macro processor model

The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.

Ultra-Fast Next Generation Human Genome Sequencing Data Processing Using DRAGEN^TMBio-IT Processor for Precision Medicine

Slow speed of the Next-Generation sequencing data analysis, compared to the latest high throughput sequencers such as HiSeq X system, using the current industry standard genome analysis pipeline, has been the major factor of data backlog which limits the real-time use of genomic data for precision medicine. This study demonstrates the DRAGEN Bio-IT Processor as a potential candidate to remove the “Big Data Bottleneck”. DRAGENTM accomplished the variant calling, for ~40× coverage WGS data in as low as ~30 minutes using a single command, achieving the over 50-fold data analysis speed while maintaining the similar or better variant calling accuracy than the standard GATK Best Practices workflow. This systematic comparison provides the faster and efficient NGS data analysis alternative to NGS-based healthcare industries and research institutes to meet the requirement for precision medicine based healthcare.

A distributed cross-domain register filefor reconfigurable cryptographic processor

Due to the fact that the register files seriously affectthe performance and area of coarse-gained reconfigurablecryptographic processors, an efficient structure of thedistributed cross-domain register file is proposed to realize acryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performanceand high flexibility at a low area cost, a union structure withthe multi-ports access structure, i, e., a distributed cross-domain register file, is designed by analyzing the algorithmfeatures of different ciphers. Considering different algorithmrequirements of the global register files and local register files,the circuit design is realized by adopting different designparameters under TSMC （ Taiwan SemiconductorManufacturing Company） 40 nm CMOS（complementary metaloxide semiconductor） technology and compared with othersimilar works. The experimental results show that theproposed distributed cross-domain register structure caneffectively improve the performance of the unit area, of whichthe total performance of block per cycle is improved by17.79% and performance of block per cycle per area isimproved bv 117 %.

Speeding up the MATLAB complex networks package using graphic processors

The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units （GPU）. This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3x. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

A hybrid two-stage fexible flowshop scheduling problem with m identical parallel machines and a burn-in processor separately

A hybrid two-stage flowshop scheduling problem was considered which involves m identical parallel machines at Stage 1 and a burn-in processor M at Stage 2, and the makespan was taken as the minimization objective. This scheduling problem is NP-hard in general. We divide it into eight subcases. Except for the following two subcases： （1） b≥ an, max{m, B} 〈 n; （2） a1 ≤ b ≤ an, m ≤ B 〈 n, for all other subcases, their NP-hardness was proved or pointed out, corresponding approximation algorithms were conducted and their worst-case performances were estimated. In all these approximation algorithms, the Multifit and PTAS algorithms were respectively used, as the jobs were scheduled in m identical parallel machines.

Three Dimensional Simulation of Ion Thruster Plume-Spacecraft Interaction Based on a Graphic Processor Unit

Based on the three-dimensional particle-in-cell （PIC） method and Compute Unified Device Architecture （CUDA）, a parallel particle simulation code combined with a graphic processor unit （GPU） has been developed for the simulation of charge-exchange （CEX） xenon ions in the plume of an ion thruster. Using the proposed technique, the potential and CEX plasma distribution are calculated for the ion thruster plume surrounding the DS1 spacecraft at different thrust levels. The simulation results are in good agreement with measured CEX ion parameters reported in literature, and the CPU＇s results are equal to a CPU＇s. Compared with a single CPU Intel Core 2 E6300, 16-processor GPU NVIDIA GeForce 9400 GT indicates a speedup factor of 3.6 when the total macro particle number is 1.1 × 10^6. The simulation results also reveal how the back flow CEX plasma affects the spacecraft floating potential, which indicates that the plume of the ion thruster is indeed able to alleviate the extreme negative floating potentials of spacecraft in geosynchronous orbit.

Tunable microwave signal generation based on an Opto-DMD processor and a photonic crystal fiber

Frequency-tunable microwave signal generation is proposed and experimentally demonstrated with a dual-wavelength single-longitudinal-mode （SLM） erbium-doped fiber ring laser based on a digital Opto-DMD processor and four-wave mixing （FWM） in a high-nonlinear photonic crystal fiber （PCF）. The high-nonlinear PCF is employed for the generation of the FWM to obtain stable and uniform dual-wavelength oscillation. Two different short passive sub-ring cavities in the main ring cavity serve as mode filters to make SLM lasing. The two lasing wavelengths are electronically selected by loading different gratings on the Opto-DMD processor controlled with a computer. The wavelength spacing can be smartly adjusted from 0.165 nm to 1.08 nm within a tuning accuracy of 0.055 nm. Two microwave signals at 17.23 GHz and 27.47 GHz are achieved. The stability of the microwave signal is discussed. The system has the ability to generate a 137.36-GHz photonic millimeter signal at room temperature.

Experimentation of a 1-pixel bit reconfigurable ternary optical processor

A detailed experiment of 1-pixel bit reconfigurable ternary optical processor （TOP） is proposed in the paper. 42 basic operation units （BOUs） and 28 typical logic operators of the TOP are realized in the experiment. Results of the test cases elaborately cover the every combination of BOUs and all the nine inputs of ternary processor. Both the experiment process and results analysis are given in this paper. The experimental results demonstrate that the theory of reconfiguring a TOP is valid and that the reconfiguration circuitry is effective.

Design of a clustered data-driven array processor for computer vision

Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different structures for heterogeneous architecture.The long data transfer delay becomes the mainly problem to limit the processing speed for computer vision applications.For reducing data transfer delay and fasting computer vision applications,a clustered data-driven array processor is proposed.A three-level pipelining processing element is designed which supports two-buffer data flow interface and 8 bits,16 bits,32 bits subtext parallel computation.At the same time,for accelerating transcendental function computation,a four-way shared pipelining transcendental function accelerator is designed,which is based on Y-intercept adjusted piecewise linear segment algorithm.A distributed shared memory structure based on unified addressing is also employed.To verify efficiency of architecture,some image processing algorithms are implemented on proposed architecture.Simultaneously the proposed architecture has been implemented on Xilinx ZC 706 development board.The same circuitry has been synthesized using SMIC 130 nm CMOS technology.The circuitry is able to run at 100 MHz.Area is 26.58 mm2.

Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture

A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.