New DDSCR structure with high holding voltage for robust ESD applications

A novel dual direction silicon-controlled rectifier(DDSCR)with an additional P-type doping and gate(APGDDSCR)is proposed and demonstrated.Compared with the conventional low-voltage trigger DDSCR(LVTDDSCR)that has positive and negative holding voltages of 13.371 V and 14.038 V,respectively,the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device,respectively,and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for±12-V application.The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device,and the four-finger APGDDSCR can achieve positive and negative human-body model(HBM)protection capabilities of 22.281 kV and 23.45 kV,respectively,under 40-V voltage of core circuit failure,benefitting from the additional structure.The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage.Thus,a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage,it is equivalent to solving the non-uniform triggering problem of multi-finger device.The operating mechanism and the gate voltage are both discussed and verified in two-dimensional(2D)simulation and experiemnt.

Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge （ESD） in high voltage LDMOS power transistors （〉 160 V） under transmission line pulsing （TLP） and very fast transmission line pulsing （VFTLP） stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

Characterization analysis of UDSM LVTSCR under TLP stress

The characteristics of a low-voltage triggering silicon-controlled rectifier （LVTSCR） under a transmission line pulse （TLP） and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge （ESD） design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron （UDSM） LVTSCR structure under ESD stress and the improvement of TLP test technology.

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.