Design of Protograph LDPC-Coded MIMO-VLC Systems with Generalized Spatial Modulation

This paper investigates the bit-interleaved coded generalized spatial modulation(BICGSM) with iterative decoding(BICGSM-ID) for multiple-input multiple-output(MIMO) visible light communications(VLC). In the BICGSM-ID scheme, the information bits conveyed by the signal-domain(SiD) symbols and the spatial-domain(SpD) light emitting diode(LED)-index patterns are coded by a protograph low-density parity-check(P-LDPC) code. Specifically, we propose a signal-domain symbol expanding and re-allocating(SSER) method for constructing a type of novel generalized spatial modulation(GSM) constellations, referred to as SSERGSM constellations, so as to boost the performance of the BICGSM-ID MIMO-VLC systems.Moreover, by applying a modified PEXIT(MPEXIT) algorithm, we further design a family of rate-compatible P-LDPC codes, referred to as enhanced accumulate-repeat-accumulate(EARA) codes,which possess both excellent decoding thresholds and linear-minimum-distance-growth property. Both analysis and simulation results illustrate that the proposed SSERGSM constellations and P-LDPC codes can remarkably improve the convergence and decoding performance of MIMO-VLC systems. Therefore, the proposed P-LDPC-coded SSERGSM-mapped BICGSMID configuration is envisioned as a promising transmission solution to satisfy the high-throughput requirement of MIMO-VLC applications.

Doped low-density parity-check codes

In this paper,we propose a doping approach to lower the error floor of Low-Density Parity-Check(LDPC)codes.The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code.Accordingly,an algorithm for selecting the information bits of the short code is proposed,and a specific two-stage decoding algorithm is presented.Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10^(-6)Furthermore,the proposed design can lower the error floor of original LDPC Codes.

Construction of Protograph LDPC Codes Based on the Convolution Neural Network

This paper presents an intelligent protograph construction algorithm.Protograph LDPC codes have shown excellent error correction performance and play an important role in wireless communications.Random search or manual construction are often used to obtain a good protograph,but the efficiency is not high enough and many experience and skills are needed.In this paper,a fast searching algorithm is proposed using the convolution neural network to predict the iterative decoding thresholds of protograph LDPC codes effectively.A special input data transformation rule is applied to provide stronger generalization ability.The proposed algorithm converges faster than other algorithms.The iterative decoding threshold of the constructed protograph surpasses greedy algorithm and random search by about 0.53 dB and 0.93 dB respectively under 100 times of density evolution.Simulation results show that quasi-cyclic LDPC(QC-LDPC)codes constructed from the proposed algorithm have competitive performance compared to other papers.

一种LDPC码的优化分层阈值偏移最小和译码算法

针对低密度奇偶校验(Low-Density Parity-Check,LDPC)码的译码算法在高信噪比区域性能较差和传统的泛洪调度译码方式收敛速度较慢等问题,提出了一种优化的分层阈值偏移最小和(Improved Layered Threshold Offset Min-Sum,ILTOMS)LDPC译码算法。该算法通过在最小值近零处添加一个阈值,在最小值小于该阈值的情况下选择局部最优的算法规避偏移最小和(Offset Min-Sum,OMS)译码算法的归零损失,在最小值较大时设置一个阈值来改善高信噪比时的译码性能,并且采用分层调度的方式进一步提高译码性能。仿真结果表明,所提的ILTOMS译码算法在复杂度无明显变化的情况下有一定性能增益,相比其他两种译码算法译码性能分别提升了0.4 dB和0.45 dB。

基于可靠度差值特征的自适应判决多元LDPC译码算法

利用变量节点符号可靠度在迭代过程中的分布特征,提出了一种基于可靠度差值特征的自适应判决多元低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。整个迭代过程划分为两个阶段,针对不同阶段节点可靠度的差值特征分别采用不同的判决策略:前期阶段,采用传统的基于最大可靠度的判决策略;后期阶段,根据最大、次大可靠度之间的差值特征,设计自适应的码元符号判决策略。仿真结果表明,所提算法在相当的译码复杂度前提下,能获得0.15~0.4 dB的性能增益。同时,对于列重较小的LDPC码,具有更低的译码错误平层。

一种非规则广义LDPC码的构造方法

广义低密度奇偶校验(Generalized Low-Density Parity-Check, GLDPC)码把低密度奇偶校验(Low-Density Parity-Check, LDPC)码中的单奇偶校验(Single Parity-Check, SPC)节点替换为校验能力更强的广义约束(Generalized Constraint, GC)节点,使其在中短码和低码率的条件下具有更低的误码率。传统GLDPC码要求基矩阵的行重等于分量码的码长,这限制了GLDPC码构造的灵活性。另外,相比于传统GLDPC码中GC节点位置的随机选取,GC节点的位置选择在GLDPC码的误码率性能上有一定的优化空间。针对以上两点,提出了一种基于渐进边增长(Progressive Edge-Growth, PEG)算法的非规则GLDPC码构造方法和一种基于Tanner图边数的GC节点位置选择算法。使用PEG算法生成的非规则LDPC码作为本地码,根据本地码的校验节点度使用多种分量码,结合GC节点位置选择算法构造非规则GLDPC码。仿真结果表明,与传统方法构造的GLDPC码相比,基于Tanner图边数的GC节点位置选择算法构造的非规则PEG-GLDPC码在误码率和译码复杂度上均得到明显改善。

基于分层最小和译码的RS-LDPC级联码改进算法

RS-LDPC级联码能够有效提高数据传输的可靠性和系统的容错能力,在5G通信等领域中得到了广泛的应用,且在6G中具有很好的应用前景。但是RS-LDPC级联码与单码相比具有计算复杂度高、不易于在硬件上实现的不足,因此提出一种基于分层最小和的RS-LDPC级联码改进译码算法,将LDPC码的校验矩阵分解成多个子矩阵,在不同子矩阵层次上并行计算。此外,还引入了新的关于校验节点信息更新的简化函数,旨在保证译码性能的同时降低计算复杂度,达到易于硬件实现的目的。结果表明改进型分层最小和算法复杂度大大降低,且在性能上优于传统BP译码0.25 dB左右。

基于阿贝尔群上的差分集构造LDPC码

本文给出了区组长度为3、4和5的平衡不完全区组设计,将设计的关联矩阵作为校验矩阵,从而构造出3种低密度奇偶校验码(LDPC,low-density parity-check code)。由于这些校验矩阵是准循环矩阵,所以构造的码是拟循环LDPC码(QC-LDPC,quasi-cyclic LDPC)。计算码的相关参数,并针对具体的例子通过与类随机码的译码性能进行分析比较,结果显示,所构造的码具有较好的性能。

Efficient construction and encoding of QC-LDPC codes by cyclic lifting of protographs

Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.

Construction of protograph LDPC codes with circular generator matrices

The application of protograph low density parity check （LDPC） codes involves the encoding complexity problem. Since the generator matrices are dense, and if the positions of ＂1＂ s are irregularity, the encoder needs to store every ＂1＂ of the generator matrices by using huge chip area. In order to solve this problem, we need to design the protograph LDPC codes with circular generator matrices. A theorem concerning the circulating property of generator matrices of nonsingular protograph LDPC codes is proposed. The circulating property of generator matrix of nonsingular protograph LDPC codes can be obtained from the corresponding quasi-cyclic parity check matrix. This paper gives a scheme of constructing protograph LDPC codes with circulating generator matrices, and it reveals that the fast encoding algorithm of protograph LDPC codes has lower encoding complexity under the condition of the proposed theorem. Simulation results in ad- ditive white Gaussian noise （AWGN） channels show that the bit error rate （BER） performance of the designed codes based on the proposed theorem is much better than that of GB20600 LDPC codes and Tanner LDPC codes.

Relative-Residual-Based Dynamic Schedule for Belief Propagation Decoding of LDPC Codes

Two Relative-Residual-based Dynamic Schedules(RRDS) for Belief Propagation(BP) decoding of Low-Density Parity-Check(LDPC) codes are proposed,in which the Variable code-RRDS(VN-RRDS) is a greediness-reduced version of the Check code-RRDS(CN-RRDS).The RRDS only processes the variable(or check) node,which has the maximum relative residual among all the variable(or check) nodes in each decoding iteration,thus keeping less greediness and decreased complexity in comparison with the edge-based Variable-to-Check Residual Belief Propagation(VC-RBP) algorithm.Moreover,VN-RRDS propagates first the message which has the largest residual based on all check equations.For different types of LDPC codes,simulation results show that the convergence rate of RRDS is higher than that of VC-RBP while keeping very low computational complexity.Furthermore,VN-RRDS achieves faster convergence as well as better performance than CN-RRDS.

DESIGN OF QUASI-CYCLIC LDPC CODES BASED ON EUCLIDEAN GEOMETRIES

A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.

Low-Density Parity-Check Codes:Highway to Channel Capacity

Low-density parity-check(LDPC)codes are not only capacity-approaching,but also greatly suitable for high-throughput implementation.Thus,they are the most popular codes for high-speed data transmission in the past two decades.Thanks to the low-density property of their parity-check matrices,the optimal maximum a posteriori probability decoding of LDPC codes can be approximated by message-passing decoding with linear complexity and highly parallel nature.Then,it reveals that the approximation has to carry on Tanner graphs without short cycles and small trapping sets.Last,it demonstrates that well-designed LDPC codes with the aid of computer simulation and asymptotic analysis tools are able to approach the channel capacity.Moreover,quasi-cyclic(QC)structure is introduced to significantly facilitate their high-throughput implementation.In fact,compared to the other capacity-approaching codes,QC-LDPC codes can provide better area-efficiency and energy-efficiency.As a result,they are widely applied in numerous communication systems,e.g.,Landsat satellites,Chang’e Chinese Lunar mission,5G mobile communications and so on.What’s more,its extension to non-binary Galois fields has been adopted as the channel coding scheme for BeiDou navigation satellite system.

Construction of time-frequency codes based on protograph LDPC codes in OFDM communication systems

This paper proposes a scheme to construct time- frequency codes based on protograph low density parity check （LDPC） codes in orthogonal frequency division multiplexing （OFDM） communication systems. This approach synthesizes two techniques： protograph LDPC codes and OFDM. One symbol of encoded information by protograph LDPC codes corresponds to one sub-carrier, namely the length of encoded information equals to the number of sub-carriers. The design of good protograph LDPC codes with short lengths is given, and the proposed proto- graph LDPC codes can be of fast encoding, which can reduce the encoding complexity and simplify encoder hardware implementa- tion. The proposed approach provides a higher coding gain in the Rayleigh fading channel. The simulation results in the Rayleigh fading channel show that the bit error rate （BER） performance of the proposed time-frequency codes is as good as random LDPC- OFDM codes and is better than Tanner LDPC-OFDM codes under the condition of different fading coefficients.

PERFORMANCE OF SIMPLE-ENCODING IRREGULAR LDPC CODES BASED ON SPARSE GENERATOR MATRIX

A new method for the construction of the high performance systematic irregular low-density paritycheck （LDPC） codes based on the sparse generator matrix （G-LDPC） is introduced. The code can greatly reduce the encoding complexity while maintaining the same decoding complexity as traditional regular LDPC （H-LDPC） codes defined by the sparse parity check matrix. Simulation results show that the performance of the proposed irregular LDPC codes can offer significant gains over traditional LDPC codes in low SNRs with a few decoding iterations over an additive white Gaussian noise （AWGN） channel.

Weighted symbol-flipping decoding algorithm for nonbinary LDPC codes with flipping patterns

A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.

Combinatorial design-based quasi-cyclic LDPC codes with girth eight

This paper presents a novel regular Quasi-Cyclic (QC)Low Density Parity Check (LDPC)codes with columnweight three and girth at least eight.These are designed on the basis of combinatorial design in which subsets applied for the construction of circulant matrices are determined by a particular subset.Considering the nonexistence of cycles four and six in the structure of the parity check matrix,a bound for their minimum weight is proposed.The simtdations conducted confirm that without applying a masking technique,the newly implemented codes have a performance similar to or better than other well-known codes.This is evident in the waterfall region, while their error floor at very low Bit Error Rate (BER)is expected.

Construction of LDPC Codes for the Layered Decoding Algorithm

Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,

Lowering the Error Floor of ADMM Penalized Decoder for LDPC Codes

Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.

Irregular and regular LDPC codes with high spectrum efficiency modulation in image transmission over fading channel

If the degree distribution is chosen carefully, the irregular low-density parity-check (LDPC) codes can outperform the regular ones. An image transmission system is proposed by combining regular and irregular LDPC codes with 16QAM/64QAM modulation to improve both efficiency and reliability. Simulaton results show that LDPC codes are good coding schemes over fading channel in image communication with lower system complexity. More over, irregular codes can obtain a code gain of about 0.7 dB compared with regular ones when BER is 10 -4. So the irregular LDPC codes are more suitable for image transmission than the regular codes.