A 4. 224GHz quadrature voltage-controlled oscillator (QVCO) applied in MB-OFDM UWB synthesizers is implemented in 0.18μm RF-CMOS technology. An improved structure of the QVCO is presented for better phase noise. A ...A 4. 224GHz quadrature voltage-controlled oscillator (QVCO) applied in MB-OFDM UWB synthesizers is implemented in 0.18μm RF-CMOS technology. An improved structure of the QVCO is presented for better phase noise. A novel configuration of a MOS varactor is designed for good linearity of K as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron. Measurement results show a phase noise of - 90.4dBc/Hz at 100kHz offset and - 116.7dBc/Hz at 1MHz offset from a carrier close to 4. 224GHz. The power dissipation is 10. 55mW from a 1.8V supply.展开更多
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator (QVCO) is employed to generate quadrature (I/Q) signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,an...A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,and a two stage ring VCO.The principle of this VCO is demonstrated and further the phase noise is discussed in detail.The fabrication of prototype is demonstrated using 0 25μm single poly five metal N well salicide CMOS digital process.The reports show that the novel VCO is can generate quadrature LO signals with a tuning range of more than 300MHz as well as the phase noise--104 33dBc/Hz at 600KHz offset at 2 41GHz (when measuring only one port of differential outputs).In addition,this VCO can work in low power supply voltage and dissipate low power,thus it can be used in many integrated transceivers.展开更多
This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communicatio...This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.展开更多
文摘A 4. 224GHz quadrature voltage-controlled oscillator (QVCO) applied in MB-OFDM UWB synthesizers is implemented in 0.18μm RF-CMOS technology. An improved structure of the QVCO is presented for better phase noise. A novel configuration of a MOS varactor is designed for good linearity of K as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron. Measurement results show a phase noise of - 90.4dBc/Hz at 100kHz offset and - 116.7dBc/Hz at 1MHz offset from a carrier close to 4. 224GHz. The power dissipation is 10. 55mW from a 1.8V supply.
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator (QVCO) is employed to generate quadrature (I/Q) signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
文摘A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,and a two stage ring VCO.The principle of this VCO is demonstrated and further the phase noise is discussed in detail.The fabrication of prototype is demonstrated using 0 25μm single poly five metal N well salicide CMOS digital process.The reports show that the novel VCO is can generate quadrature LO signals with a tuning range of more than 300MHz as well as the phase noise--104 33dBc/Hz at 600KHz offset at 2 41GHz (when measuring only one port of differential outputs).In addition,this VCO can work in low power supply voltage and dissipate low power,thus it can be used in many integrated transceivers.
基金Project supported by the Chinese National High-Tech Research and Development Program(Nos2009ZX03007-001,2009AA011606)the National Natural Science Foundation of China(No60976023)
文摘This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.