An injection-Locked divider(ILD)can provide good synchronization at lower inputsignal to noise ratio,which is its advantage over other types of divider.The general expressionof phase equation and equivalent model are ...An injection-Locked divider(ILD)can provide good synchronization at lower inputsignal to noise ratio,which is its advantage over other types of divider.The general expressionof phase equation and equivalent model are presented for the ILD with an input additive noise.In the absence of noise the performance of the phase-modulated signal through the ILD andsynchronous ranges of the ILD are given.The effects of the additive noise on the ILD arediscuued.The injection-locked amplifier(ILA)is only a particular case in which n=1,thereforethe given results arc applicable to the ILA.展开更多
This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the IL...This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.展开更多
In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extend...In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.展开更多
The goal here is to give a simple approach to a quadrature formula based on the divided diffierences of the integrand at the zeros of the nth Chebyshev polynomial of the first kind,and those of the(n-1)st Chebyshev po...The goal here is to give a simple approach to a quadrature formula based on the divided diffierences of the integrand at the zeros of the nth Chebyshev polynomial of the first kind,and those of the(n-1)st Chebyshev polynomial of the second kind.Explicit expressions for the corresponding coefficients of the quadrature rule are also found after expansions of the divided diffierences,which was proposed in[14].展开更多
The aim of this work is to construct a new quadrature formula for Fourier Chebyshev coef ficients based on the divided differences of the integrand at points 1, 1 and the zeros of the n th Chebyshev polynomial o...The aim of this work is to construct a new quadrature formula for Fourier Chebyshev coef ficients based on the divided differences of the integrand at points 1, 1 and the zeros of the n th Chebyshev polynomial of the second kind. The interesting thing is that this quadrature rule is closely related to the well known Gauss Turn quadrature formula and similar to a recent result of Micchelli and Sharma, extending a particular case due to Micchelli and Rivlin.展开更多
We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is...We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.展开更多
A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The trequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals. Compared with convention...A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The trequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals. Compared with conventional dividers, the circuit achieves an output 1/Q phase sequence that is independent of the input I/Q phase sequence. Moreover, the third harmonic is effectively suppressed by employing a double degeneration technique. The design is fabricated in TSMC 0.13-#m CMOS and operated at 1.2 V. While locked at 8.5 GHz, the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset. The circuit achieves a locking range of 15% while consuming a total current of 4.5 mA.展开更多
This paper presents the design of a low power （LP） and a low noise figure （NF） quadrature demodula- tor with an on-chip frequency divider for quadrature local oscillator （LO） signal generation. The transconducta...This paper presents the design of a low power （LP） and a low noise figure （NF） quadrature demodula- tor with an on-chip frequency divider for quadrature local oscillator （LO） signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demod- ulator is designed for an input radio frequency （RF） band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency （IF） band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain （VCG） ranging from 14.2 to 13.2 dB, and a minimum single-sideband N F （SSB-NF） of 9 dB. The measured third-order input intercept point （lIP3） is -3.3 dBm lbr a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-rim LP CMOS technology, are also presented in this paper.展开更多
文摘An injection-Locked divider(ILD)can provide good synchronization at lower inputsignal to noise ratio,which is its advantage over other types of divider.The general expressionof phase equation and equivalent model are presented for the ILD with an input additive noise.In the absence of noise the performance of the phase-modulated signal through the ILD andsynchronous ranges of the ILD are given.The effects of the additive noise on the ILD arediscuued.The injection-locked amplifier(ILA)is only a particular case in which n=1,thereforethe given results arc applicable to the ILA.
文摘This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.
文摘In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.
基金Supported by the National Natural Science Foundation of China（10571121） Supported by the Natural Science Foundation of Guangdong Province（5010509）
文摘The goal here is to give a simple approach to a quadrature formula based on the divided diffierences of the integrand at the zeros of the nth Chebyshev polynomial of the first kind,and those of the(n-1)st Chebyshev polynomial of the second kind.Explicit expressions for the corresponding coefficients of the quadrature rule are also found after expansions of the divided diffierences,which was proposed in[14].
文摘The aim of this work is to construct a new quadrature formula for Fourier Chebyshev coef ficients based on the divided differences of the integrand at points 1, 1 and the zeros of the n th Chebyshev polynomial of the second kind. The interesting thing is that this quadrature rule is closely related to the well known Gauss Turn quadrature formula and similar to a recent result of Micchelli and Sharma, extending a particular case due to Micchelli and Rivlin.
基金Project supported by the National Basic Research Program(973)of China(No.2010CB327404)the National High-Tech R&D Program(863)of China(No.2011AA10305)the National Natural Science Foundation of China(Nos.60901012 and 61106024)
文摘We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.
基金Project supported by the National Sci&Tech Major Projects of China(Nos.2009ZX03006-007-01,2009ZX03007-001,2009ZX03006- 009)the National High Tech R&D Program of China(No.2009AA01Z261)
文摘A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The trequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals. Compared with conventional dividers, the circuit achieves an output 1/Q phase sequence that is independent of the input I/Q phase sequence. Moreover, the third harmonic is effectively suppressed by employing a double degeneration technique. The design is fabricated in TSMC 0.13-#m CMOS and operated at 1.2 V. While locked at 8.5 GHz, the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset. The circuit achieves a locking range of 15% while consuming a total current of 4.5 mA.
基金supported by the National High Technology Research and Development Program of China(No.2011AA010200)
文摘This paper presents the design of a low power （LP） and a low noise figure （NF） quadrature demodula- tor with an on-chip frequency divider for quadrature local oscillator （LO） signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demod- ulator is designed for an input radio frequency （RF） band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency （IF） band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain （VCG） ranging from 14.2 to 13.2 dB, and a minimum single-sideband N F （SSB-NF） of 9 dB. The measured third-order input intercept point （lIP3） is -3.3 dBm lbr a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-rim LP CMOS technology, are also presented in this paper.
