A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achiev...A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature（I/Q） local oscillating signal.A high-speed 8/9 dual-modulus prescaler（DMP）,a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm^2.展开更多
A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC...A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC） 65nm complementary metal-oxide-semiconductor （CMOS） technology. A novel quadrature voltage-controlled-oscillator （QVCO） structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence （PRBS） input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW （excluding output buffers）.展开更多
文摘A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature（I/Q） local oscillating signal.A high-speed 8/9 dual-modulus prescaler（DMP）,a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm^2.
基金supported by the Communication Systems Project of Jiangsu Department (JHB04010)the National Natural Science Foundation of China (60976029)
文摘A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC） 65nm complementary metal-oxide-semiconductor （CMOS） technology. A novel quadrature voltage-controlled-oscillator （QVCO） structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence （PRBS） input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW （excluding output buffers）.
