An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage ...An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.展开更多
In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loo...In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.展开更多
文摘An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.
基金supported by the National Natural Science Foundation of China under Grant 62274189the Natural Science Foundation of Guangdong Province,China,under Grant 2022A1515011054the Key Area R&D Program of Guangdong Province under Grant 2022B0701180001.
文摘In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.
文摘提出了一种集成于射频芯片的低噪声、快速建立的低压差线性稳压器(LDO)。分析了传统LDO的主要噪声源,在综合考虑芯片的噪声、静态电流和面积后,采用超低频低通滤波器,对LDO的输出噪声进行优化。基于SMIC 0.18μm工艺,采用Cadence软件对电路进行仿真。结果表明,10 Hz到100 k Hz之间的输出积分噪声电压为17μV,建立时间小于18μs,总静态电流为24μA,满足LDO的应用要求。
