With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Curren...With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.展开更多
Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventu...Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.展开更多
This paper presents a single event transient(SET) suppressor circuit,which can suppress the effect of SET in charge pump(CP) on the whole PLL frequency synthesizers,and at the same time it brings little negative effec...This paper presents a single event transient(SET) suppressor circuit,which can suppress the effect of SET in charge pump(CP) on the whole PLL frequency synthesizers,and at the same time it brings little negative effect to the system during normal operation.Because the proposed SET suppressor circuit only includes a resistor,a PMOS and an NMOS device,little area penalty is introduced.By preventing SET propagating from CP to low pass filter(LPF) and VCO when a single event strikes on CP output node,the system shows excellent hardness to SET in CP.Mixed simulations are performed on TCAD workbench.The results show that a single event with an LET at 80 MeV cm 2 /mg can only induce approximately 2.3 mV disturbance on the control voltage of VCO.展开更多
This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation.In order to improve its radiation tolerant abilities,circuit-level and device-leve...This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation.In order to improve its radiation tolerant abilities,circuit-level and device-level RHBD（radiation-hardening by design） techniques were employed.Adaptive slope compensation was used to improve the inherent instability.The H-gate MOS transistors,annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose.A boost converter was fabricated by a standard commercial 0.35μm CMOS process.The hardened design converter can work properly in a wide range of total dose radiation environments,with increasing total dose radiation.The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.展开更多
在纳米数字锁存器中,多节点翻转(multiple-node upset,MNU)正持续增加.虽然现有基于互连单元的抗辐射加固设计(radiation hardening by design,RHBD)的锁存器可以恢复所有MNU,但是需要更多的敏感节点和晶体管.为了在获得高可靠性的同时...在纳米数字锁存器中,多节点翻转(multiple-node upset,MNU)正持续增加.虽然现有基于互连单元的抗辐射加固设计(radiation hardening by design,RHBD)的锁存器可以恢复所有MNU,但是需要更多的敏感节点和晶体管.为了在获得高可靠性的同时降低硬件开销,提出利用辐射翻转机制进行加固的方法.首先,通过使用屏蔽晶体管减少敏感节点,进而降低使用的晶体管数;然后,将2个单元内的上拉晶体管进行交叉互连,从而构造出一个可抗MNU翻转的RHBD锁存器.在65 nm工艺下,与现有基于互连技术的RHBD锁存器相比,提出的RHBD锁存器可平均减少12.82%的面积,319.22%的延迟和10.66%的功耗.展开更多
A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a...A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.展开更多
微电子抗辐射设计加固(Radiation Hardening By Design,RHBD)是指在电路设计中采用特殊版图或电路结构达到抗辐射电路的性能要求,且该电路应能使用标准商用生产线的工艺技术进行制造。论述了几种采用SiGe异质结双极晶体管(HBT)的逻辑电...微电子抗辐射设计加固(Radiation Hardening By Design,RHBD)是指在电路设计中采用特殊版图或电路结构达到抗辐射电路的性能要求,且该电路应能使用标准商用生产线的工艺技术进行制造。论述了几种采用SiGe异质结双极晶体管(HBT)的逻辑电路设计加固技术。展开更多
基金The Open Project Program of the Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems(2023SZKF17)the University Synergy Innovation Program of Anhui Province(GXXT-2022-080)。
文摘With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
基金supported by the National Natural Science Foundation of China (Nos. 60633060, 60876028).
文摘Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.
基金supported by the Nation Twelfth Five-Year Plan (Grant No.11015131)
文摘This paper presents a single event transient(SET) suppressor circuit,which can suppress the effect of SET in charge pump(CP) on the whole PLL frequency synthesizers,and at the same time it brings little negative effect to the system during normal operation.Because the proposed SET suppressor circuit only includes a resistor,a PMOS and an NMOS device,little area penalty is introduced.By preventing SET propagating from CP to low pass filter(LPF) and VCO when a single event strikes on CP output node,the system shows excellent hardness to SET in CP.Mixed simulations are performed on TCAD workbench.The results show that a single event with an LET at 80 MeV cm 2 /mg can only induce approximately 2.3 mV disturbance on the control voltage of VCO.
基金Project supported by the National Defense Pre-Research Project of China(No.51311050202)
文摘This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation.In order to improve its radiation tolerant abilities,circuit-level and device-level RHBD（radiation-hardening by design） techniques were employed.Adaptive slope compensation was used to improve the inherent instability.The H-gate MOS transistors,annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose.A boost converter was fabricated by a standard commercial 0.35μm CMOS process.The hardened design converter can work properly in a wide range of total dose radiation environments,with increasing total dose radiation.The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.
文摘A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.
