New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation

The microwave plasma oxidation under the relatively high pressure(6 kPa)region is introduced into the fabrication process of SiO2/4 H-SiC stack.By controlling the oxidation pressure,species,and temperature,the record low density of interface traps(~4×10^(10)cm^(-2)·eV^(-1)@Ec-0.2 eV)is demonstrated on SiO2/SiC stack formed by microwave plasma oxidation.And high quality SiO2 with very flat interface(0.27-nm root-mean-square roughness)is obtained.High performance Si C metal–oxide–semiconductor field-effect transistors(MOSFETs)with peak field effect mobility of 44 cm^(-2)·eV^(-1)is realized without additional treatment.These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.

FORWARD GATED-DIODE METHOD FOR DIRECTLY MEASURING STRESS-INDUCED INTERFACE TRAPS IN NMOSFET/SOI

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of △Nit-t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.

Method of evaluating interface traps in Al2O3/AlGaN/GaN high electron mobility transistors

In this paper, the interface states of the AlGaN/GaN metal–insulator–semiconductor(MIS) high electron mobility transistors(HEMTs) with an Al2 O3 gate dielectric are systematically evaluated. By frequency-dependent capacitance and conductance measurements, trap density and time constant at Al2 O3/AlGaN and AlGaN/GaN interface are determined.The experimental results reveal that the density of trap states and the activation energy at the Al2 O3/AlGaN interface are much higher than at the AlGaN/GaN interface. The photo-assisted capacitance-voltage measurements are performed to characterize the deep-level traps located near mid-gap at the Al2 O3/AlGaN interface, which indicates that a density of deep-level traps is lower than the density of the shallow-level states.

Effects of stress conditions on the generation of negative bias temperature instability-associated interface traps

The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.

FORWARD GATED-DIODE METHOD FOR EXTRACTING HOT-CARRIER-STRESS-INDUCED BACK INTERFACE TRAPS IN SOI/NMOSFETs

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.

A graphical user interface(GUI)for model-based radiation-induced acoustic computed tomography

Radiation-induced acoustic computed tomography(RACT)is an evolving biomedical imaging modality that aims to reconstruct the radiation energy deposition in tissues.Traditional backprojection(BP)reconstructions carry noisy and limited-view artifacts.Model-based algorithms have been demonstrated to overcome the drawbacks of BPs.However,model-based algorithms are relatively more complex to develop and computationally demanding.Furthermore,while a plethora of novel algorithms has been developed over the past decade,most of these algorithms are either not accessible,readily available,or hard to implement for researchers who are not well versed in programming.We developed a user-friendly MATLAB-based graphical user interface(GUI;RACT2D)that facilitates back-projection and model-based image reconstructions for twodimensional RACT problems.We included numerical and experimental X-ray-induced acoustic datasets to demonstrate the capabilities of the GUI.The developed algorithms support parallel computing for evaluating reconstructions using the cores of the computer,thus further accelerating the reconstruction speed.We also share the MATLAB-based codes for evaluating RACT reconstructions,which users with MATLAB programming expertise can further modify to suit their needs.The shared GUI and codes can be of interest to researchers across the globe and assist them in e±cient evaluation of improved RACT reconstructions.

Numerical Analysis of Characterized Back Interface Trapsof SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.

Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO

Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.

Energy Dependence of Interface Trap Density——Investigated by Relaxation Spectral Technique

According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm MOSFET.And thus the energy distribution of interface trap can be determined.According to the two methods,the energy profile of interface traps agrees with those reported in literature.Compared to other methods,this method is simpler and more convenient.

A Method to Separate Effects of Oxide-Trapped Charge and Interface-Trapped Charge on Threshold Voltage in pMOSFETs Under Hot-Carrier Stress

A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.

Interface and border trapping effects in normally-off Al2O3/AlGaN/GaN MOS-HEMTs with different post-etch surface treatments

Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 10^12 cm^−2 and 6.35 × 10^12 cm^−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.

Electronic relaxation of deep bulk trap and interface state in ZnO ceramics

This paper investigates the electronic relaxation of deep bulk trap and interface state in ZnO ceramics based on dielectric spectra measured in a wide range of temperature, frequency and bias, in addition to the steady state response. It discusses the nature of net current flowing over the barrier affected by interface state, and then obtains temperature-dependent barrier height by approximate calculation from steady I-V （current-voltage） characteristics. Additional conductance and capacitance arising from deep bulk trap relaxation are calculated based on the displacement of the cross point between deep bulk trap and Fermi level under small AC signal. From the resonances due to deep bulk trap relaxation on dielectric spectra, the activation energies are obtained as 0.22 eV and 0.35 eV, which are consistent with the electronic levels of the main defect interstitial Zn and vacancy oxygen in the depletion layer. Under moderate bias, another resonance due to interface relaxation is shown on the dielectric spectra. The DC-like conductance is also observed in high temperature region on dielectric spectra, and the activation energy is much smaller than the barrier height in steady state condition, which is attributed to the displacement current coming from the shallow bulk trap relaxation or other factors.

Modeling of tunneling current in ultrathin MOS structure with interface trap charge and fixed oxide charge

A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structure. In this model, the influences of interface trap charge （ITC） at the Si-SiO2 interface and fixed oxide charge （FOC） in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.

Negative bias-induced threshold voltage instability and zener/interface trapping mechanism in GaN-based MIS-HEMTs

We investigate the instability of threshold voltage in D-mode MIS-HEMT with in-situ SiN as gate dielectric under different negative gate stresses.The complex non-monotonic evolution of threshold voltage under the negative stress and during the recovery process is induced by the combination effect of two mechanisms.The effect of trapping behavior of interface state at SiN/AlGaN interface and the effect of zener traps in AlGaN barrier layer on the threshold voltage instability are opposite to each other.The threshold voltage shifts negatively under the negative stress due to the detrapping of the electrons at SiN/AlGaN interface,and shifts positively due to zener trapping in AlGaN barrier layer.As the stress is removed,the threshold voltage shifts positively for the retrapping of interface states and negatively for the thermal detrapping in AlGaN.However,it is the trapping behavior in the AlGaN rather than the interface state that results in the change of transconductance in the D-mode MIS-HEMT.

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.

Research of Trap and Electron Density Distributions in the Interface of Polyimide/Al2O3 Nanocomposite Films Based on IDC and SAXS

The distributions of traps and electron density in the interfaces between polyimide （PI） matrix and Al2O3 nanoparticles are researched using the isothermal decay current and the small-angle x-ray scattering （SAXS） tests. According to the electron density distribution for quasi two-phase mixture doped by spherical nanoparticles, the electron densities in the interfaces of PI/Al2O3 nanocomposite films are evaluated. The trap level density and carrier mobility in the interface are studied. The experimental results show that the distribution and the change rate of the electron density in the three layers of interface are different, indicating different trap distributions in the interface layers. There is a maximum trap level density in the second layer, where the maximum trap level density for the nanocomposite film doped by 25 wt% is 1.054 × 10^22 eV·m^-3 at 1.324eV, resulting in the carrier mobility reducing. In addition, both the thickness and the electron density of the nanocomposite film interface increase with the addition of the doped Al2O3 contents. Through the study on the trap level distribution in the interface, it is possible to further analyze the insulation mechanism and to improve the performance of nano-dielectric materials.

Two-dimensional analysis of the interface state effect on current gain for a 4H-SiC bipolar junction transistor

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.

Enhanced interface properties of diamond MOSFETs with Al2O3 gate dielectric deposited via ALD at a high temperature

The interface state of hydrogen-terminated(C-H)diamond metal-oxide-semiconductor field-effect transistor(MOSFET)is critical for device performance.In this paper,we investigate the fixed charges and interface trap states in C-H diamond MOSFETs by using different gate dielectric processes.The devices use Al_(2)O_(3) as gate dielectrics that are deposited via atomic layer deposition(ALD)at 80℃and 300℃,respectively,and their C-V and I-V characteristics are comparatively investigated.Mott-Schottky plots(1/C2-VG)suggest that positive and negative fixed charges with low density of about 10^(11)cm^(-2) are located in the 80-℃-and 300-℃deposition Al2O3 films,respectively.The analyses of direct current(DC)/pulsed I-V and frequency-dependent conductance show that the shallow interface traps(0.46 eV-0.52 eV and 0.53 eV-0.56 eV above the valence band of diamond for the 80-℃and 300-℃deposition conditions,respectively)with distinct density(7.8×10^(13)eV^(-1)·cm^(-2)-8.5×10^(13)eV^(-1)·cm^(-2) and 2.2×10^(13)eV^(-1)·cm^(-2)-5.1×10^(13)eV^(-1)·cm^(-2) for the 80-℃-and 300-℃-deposition conditions,respectively)are present at the Al2O3/C-H diamond interface.Dynamic pulsed I-V and capacitance dispersion results indicate that the ALD Al_(2)O_(3) technique with 300-℃deposition temperature has higher stability for C-H diamond MOSFETs.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.