This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. ...This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin（RSNM） due to the bit-line isolation during the read. Static noise margins for data read（RSNM）, write（WSNM）, read delay, write delay, data retention voltage（DRV）, leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.展开更多
Multilevel ferroelectric field-effect transistors(FeFETs)integrated with HfO_(2)-based ferroelectric thin films demonstrate tremendous potential in high-speed massive data storage and neuromorphic computing applicatio...Multilevel ferroelectric field-effect transistors(FeFETs)integrated with HfO_(2)-based ferroelectric thin films demonstrate tremendous potential in high-speed massive data storage and neuromorphic computing applications.However,few works have focused on the stability of the multiple memory states in the HfO_(2)-based FeFETs.Here we firstly report the write/read disturb effects on the multiple memory states in the Hf_(0.5)Zr_(0.5)O_(2)(HZO)-based FeFETs.The multiple memory states in HZO-based FeFETs do not show obvious degradation with the write and read disturb cycles.Moreover,the retention characteristics of the intermediate memory states in HZO-based FeFETs with unsaturated ferroelectric polarizations are better than that of the memory state with saturated ferroelectric polarization.Through the deep analysis of the operation principle of in HZO-based FeFETs,we speculate that the better retention properties of intermediate memory states are determined by the less ferroelectric polarization degradation and the weaker ferroelectric polarization shielding.The experimental and theoretical evidences confirm that the long-term stability of the intermediate memory states in HZO-based FeFETs are as robust as that of the saturated memory state,laying a solid foundation for their practical applications.展开更多
文摘This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin（RSNM） due to the bit-line isolation during the read. Static noise margins for data read（RSNM）, write（WSNM）, read delay, write delay, data retention voltage（DRV）, leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.
基金This work was partly supported by the National Natural Science Foundation of China(Grant Nos.52122205,51902274,52072324,and 11932016)the Science and Technology Innovation Program of Hunan Province(Grant No.2020RC2077)the Natural Science Foundation of Hunan Province(Grant No.2019JJ50617).
文摘Multilevel ferroelectric field-effect transistors(FeFETs)integrated with HfO_(2)-based ferroelectric thin films demonstrate tremendous potential in high-speed massive data storage and neuromorphic computing applications.However,few works have focused on the stability of the multiple memory states in the HfO_(2)-based FeFETs.Here we firstly report the write/read disturb effects on the multiple memory states in the Hf_(0.5)Zr_(0.5)O_(2)(HZO)-based FeFETs.The multiple memory states in HZO-based FeFETs do not show obvious degradation with the write and read disturb cycles.Moreover,the retention characteristics of the intermediate memory states in HZO-based FeFETs with unsaturated ferroelectric polarizations are better than that of the memory state with saturated ferroelectric polarization.Through the deep analysis of the operation principle of in HZO-based FeFETs,we speculate that the better retention properties of intermediate memory states are determined by the less ferroelectric polarization degradation and the weaker ferroelectric polarization shielding.The experimental and theoretical evidences confirm that the long-term stability of the intermediate memory states in HZO-based FeFETs are as robust as that of the saturated memory state,laying a solid foundation for their practical applications.
