Low Area PRESENT Cryptography in FPGA Using TRNG-PRNG Key Generation

Lightweight Cryptography(LWC)is widely used to provide integrity,secrecy and authentication for the sensitive applications.However,the LWC is vulnerable to various constraints such as high-power consumption,time consumption,and hardware utilization and susceptible to the malicious attackers.In order to overcome this,a lightweight block cipher namely PRESENT architecture is proposed to provide the security against malicious attacks.The True Random Number Generator-Pseudo Random Number Generator(TRNG-PRNG)based key generation is proposed to generate the unpredictable keys,being highly difficult to predict by the hackers.Moreover,the hardware utilization of PRESENT architecture is optimized using the Dual port Read Only Memory(DROM).The proposed PRESENT-TRNGPRNG architecture supports the 64-bit input with 80-bit of key value.The performance of the PRESENT-TRNG-PRNG architecture is evaluated by means of number of slice registers,flip flops,number of slices Look Up Table(LUT),number of logical elements,slices,bonded input/output block(IOB),frequency,power and delay.The input retrieval performances analyzed in this PRESENT-TRNG-PRNG architecture are Peak Signal to Noise Ratio(PSNR),Structural Similarity Index(SSIM)and Mean-Square Error(MSE).The PRESENT-TRNG-PRNG architecture is compared with three different existing PRESENT architectures such as PRESENT On-TheFly(PERSENT-OTF),PRESENT Self-Test Structure(PRESENT-STS)and PRESENT-Round Keys(PRESENT-RK).The operating frequency of the PRESENT-TRNG-PRNG is 612.208 MHz for Virtex 5,which is high as compared to the PRESENT-RK.

Small Area ROM Design for Embedded Applications

The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.