Design and prototyping of the readout electronics for the transition radiation detector in the high energy cosmic radiation detection facility

The high energy cosmic-radiation detection(HERD)facility is planned to launch in 2027 and scheduled to be installed on the China Space Station.It serves as a dark matter particle detector,a cosmic ray instrument,and an observatory for high-energy gamma rays.A transition radiation detector placed on one of its lateral sides serves dual purpose,(ⅰ)calibrating HERD's electromagnetic calorimeter in the TeV energy range,and(ⅱ)serving as an independent detector for high-energy gamma rays.In this paper,the prototype readout electronics design of the transition radiation detector is demonstrated,which aims to accurately measure the charge of the anodes using the SAMPA application specific integrated circuit chip.The electronic performance of the prototype system is evaluated in terms of noise,linearity,and resolution.Through the presented design,each electronic channel can achieve a dynamic range of 0–100 fC,the RMS noise level not exceeding 0.15 fC,and the integral nonlinearity was<0.2%.To further verify the readout electronic performance,a joint test with the detector was carried out,and the results show that the prototype system can satisfy the requirements of the detector's scientific goals.

Studies of an event-building algorithm of the readout system for the twin TPCs in HFRS

The High-energy Fragment Separator(HFRS),which is currently under construction,is a leading international radioactive beam device.Multiple sets of position-sensitive twin time projection chamber(TPC)detectors are distributed on HFRS for particle identification and beam monitoring.The twin TPCs'readout electronics system operates in a trigger-less mode due to its high counting rate,leading to a challenge of handling large amounts of data.To address this problem,we introduced an event-building algorithm.This algorithm employs a hierarchical processing strategy to compress data during transmission and aggregation.In addition,it reconstructs twin TPCs'events online and stores only the reconstructed particle information,which significantly reduces the burden on data transmission and storage resources.Simulation studies demonstrated that the algorithm accurately matches twin TPCs'events and reduces more than 98%of the data volume at a counting rate of 500 kHz/channel.

Quantum generative adversarial networks based on a readout error mitigation method with fault tolerant mechanism

Readout errors caused by measurement noise are a significant source of errors in quantum circuits,which severely affect the output results and are an urgent problem to be solved in noisy-intermediate scale quantum(NISQ)computing.In this paper,we use the bit-flip averaging(BFA)method to mitigate frequent readout errors in quantum generative adversarial networks(QGAN)for image generation,which simplifies the response matrix structure by averaging the qubits for each random bit-flip in advance,successfully solving problems with high cost of measurement for traditional error mitigation methods.Our experiments were simulated in Qiskit using the handwritten digit image recognition dataset under the BFA-based method,the Kullback-Leibler(KL)divergence of the generated images converges to 0.04,0.05,and 0.1 for readout error probabilities of p=0.01,p=0.05,and p=0.1,respectively.Additionally,by evaluating the fidelity of the quantum states representing the images,we observe average fidelity values of 0.97,0.96,and 0.95 for the three readout error probabilities,respectively.These results demonstrate the robustness of the model in mitigating readout errors and provide a highly fault tolerant mechanism for image generation models.

Threshold-independent method for single-shot readout of spin qubits in semiconductor quantum dots

The single-shot readout data process is essential for the realization of high-fidelity qubits and fault-tolerant quantum algorithms in semiconductor quantum dots. However, the fidelity and visibility of the readout process are sensitive to the choice of the thresholds and limited by the experimental hardware. By demonstrating the linear dependence between the measured spin state probabilities and readout visibilities along with dark counts, we describe an alternative threshold-independent method for the single-shot readout of spin qubits in semiconductor quantum dots. We can obtain the extrapolated spin state probabilities of the prepared probabilities of the excited spin state through the threshold-independent method. We then analyze the corresponding errors of the method, finding that errors of the extrapolated probabilities cannot be neglected with no constraints on the readout time and threshold voltage. Therefore, by limiting the readout time and threshold voltage, we ensure the accuracy of the extrapolated probability. We then prove that the efficiency and robustness of this method are 60 times larger than those of the most commonly used method. Moreover, we discuss the influence of the electron temperature on the effective area with a fixed external magnetic field and provide a preliminary demonstration for a single-shot readout of up to 0.7K/1.5T in the future.

Design of a high-dynamic-range prototype readout system for VLAST calorimeter

In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-energy imaging calorimeter(HEIC) is currently being developed as a homogeneous calorimeter that utilizes long bismuth germanate(BGO) scintillation crystals as both absorbers and detectors. To accurately measure the energy deposition in the BGO bar of HEIC, a highdynamic-range readout method using a silicon photomultiplier(SiPM) and multiphotodiode(PD) with different active areas has been proposed. A prototype readout system that adopts multichannel charge measurement ASICs was also developed to read out the combined system of SiPMs and PDs. Preliminary tests confirmed the feasibility of the readout scheme, which is expected to have a dynamic range close to 10~6.

Advances in nuclear detection and readout techniques

“A Craftsman Must Sharpen His Tools to Do His Job,”said Confucius.Nuclear detection and readout techniques are the foundation of particle physics,nuclear physics,and particle astrophysics to reveal the nature of the universe.Also,they are being increasingly used in other disciplines like nuclear power generation,life sciences,environmental sciences,medical sciences,etc.The article reviews the short history,recent development,and trend of nuclear detection and readout techniques,covering Semiconductor Detector,Gaseous Detector,Scintillation Detector,Cherenkov Detector,Transition Radiation Detector,and Readout Techniques.By explaining the principle and using examples,we hope to help the interested reader underst and this research field and bring exciting information to the community.

FPGA Optimized Accelerator of DCNN with Fast Data Readout and Multiplier Sharing Strategy

With the continuous development of deep learning,Deep Convolutional Neural Network(DCNN)has attracted wide attention in the industry due to its high accuracy in image classification.Compared with other DCNN hard-ware deployment platforms,Field Programmable Gate Array(FPGA)has the advantages of being programmable,low power consumption,parallelism,and low cost.However,the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of the DCNN accelerator.The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing,but this method’s data multiplexing rate is low because it repeatedly reads the data between rows.This paper proposes a fast data readout strategy via the circular sliding window data reading method,it can improve the multiplexing rate of data between rows by optimizing the memory access order of input data.In addition,the multiplication bit width of the DCNN accelerator is much smaller than that of the Digital Signal Processing(DSP)on the FPGA,which means that there will be a waste of resources if a multiplication uses a single DSP.A multiplier sharing strategy is proposed,the multiplier of the accelerator is customized so that a single DSP block can complete multiple groups of 4,6,and 8-bit signed multiplication in parallel.Finally,based on two strategies of appeal,an FPGA optimized accelerator is proposed.The accelerator is customized by Verilog language and deployed on Xilinx VCU118.When the accelerator recognizes the CIRFAR-10 dataset,its energy efficiency is 39.98 GOPS/W,which provides 1.73×speedup energy efficiency over previous DCNN FPGA accelerators.When the accelerator recognizes the IMAGENET dataset,its energy efficiency is 41.12 GOPS/W,which shows 1.28×−3.14×energy efficiency compared with others.

Edims: an event-driven internal memory synchronized readout prototype ASIC chip developed for HFRS-TPC

HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for particle identification and beam monitoring at HFRS. This paper presents an event-driven internal memory and synchronous readout(EDIMS)prototype ASIC chip. The aim is to provide HFRS-TPC with high-precision time and charge measurements with high count rates and a large dynamic range. The first prototype EDIMS chip integrated 16 channels and is fabricated using a 0.18-μm CMOS process. Each channel consists of a charge-sensitive amplifier, fast shaper, slow shaper, peak detect-and-hold circuit, discriminator with time-walk compensation, analog memory, and FIFO. The token ring is used for clock-synchronous readout. The chip is taped and tested.

A Fully Integrated CMOS Readout Circuit for Particle Detectors

Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.

Design and implementation of GM- APD array readout circuit for infrared imaging

Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.

Readout electronics for a high-resolution soft X-ray spectrometer based on silicon drift detector

The readout electronics for a prototype soft X-ray spectrometer based on silicon drift detector(SDD),for precisely measuring the energy and arrival time of X-ray photons is presented in this paper.The system mainly consists of two parts,i.e.,an analog electronics section(including a pre-amplifier,a signal shaper and filter,a constant fraction timing circuit,and a peak hold circuit)and a digital electronics section(including an ADC and a TDC).Test results with X-ray sources show that an energy dynamic range of 1-10 keV with an integral nonlinearity of less than 0.1%can be achieved,and the energy resolution is better than 160 eV @ 5.9 keV FWHM.Using a waveform generator,test results also indicate that time resolution of the electronics system is about 3.7 ns,which is much less than the transit time spread of SDD(<100 ns)and satisfies the requirements of future applications.

Readout electronics of a prototype time-of-flight ion composition analyzer for space plasma

Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By utilizing a constant fraction discriminator(CFD) and time-to-digital converter(TDC), challenging dynamic range measurements were performed with high time resolution and event rates. CFD was employed to discriminate the TOF signals from the micro-channel plate and channel electron multipliers. TDC based on the combination of counter and OR-gate delay chain was designed in a highreliability flash field programmable gate array. Owing to the non-uniformity of the delay chain, a correction algorithm based on integral nonlinearity compensation was implemented to reduce the time uncertainty. The test results showed that the electronics achieved a low timingerror of < 200 ps in the input range from 35 to 500 m V for the CFD, and a time resolution of ～550 ps with time uncertainty < 180 ps after correction and a time range of6.4 ls for the TDC. The TOF spectrum from an electron beam experiment of the impacting N_2 gas further indicated the good performance of this readout electronic.

Geant4对强子量能器dual-readout方法的模拟研究

基于Geant4对强子量能器的dual-readout方法进行了系统的模拟研究.对模拟得到的结果采用两种方法进行了能量修正,分析其是否可实现提高强子分辨率的目标,为今后该方法的应用实现提供理论依据.

Design and evaluation of prototype readout electronics for nuclide detector in Very Large Area Space Telescope

China plans to develop the next generation dark matter particle explorer satellite,referred to as the Very Large Area Space Telescope(VLAST).As an essential step in this process,the prototype design of detectors and electronics for the VLAST is currently underway.The nuclide detector is a core detector in the VLAST.It mainly measures nuclides’charges and distinguishes high-energy gamma rays and electrons.This paper will discuss the prototype readout electronics for the VLAST’s nuclide detector,which accurately measures the charge signal of the photomultiplier tubes using the VATA160 applicationspecific integrated circuit chip;furthermore,we consider a series of critical problems,including radiation-hardening and environment monitoring.The test results show that the system exhibits stable operation,good performance,and good technical indicators.Furthermore,each electronic channel achieves a dynamic range of 0-12.5 pC,the random noise level exceeds 1.6 fC,and the integral nonlinearity exceeds 0.35%.

Performance of the CAT-TPC based on two-dimensional readout strips

A gas detector 140×140×140 mm^(3)in size,termed the compact active target time projection chamber(CAT-TPC),was developed in this study to measure resonant scattering associated with cluster structures in unstable nuclei.The CAT-TPC consists of an electronic field cage,double-thick gas-electron-multiplier foils,a general-purpose digital data acquisition system,and a newly developed two-dimensional strip-readout structure.The CAT-TPC was operated using a^(4)He(96%)+CO_(2)(4%)gas mixture at 400 mbar.The working gas also serves as an active target for tracking charged particles.The overall performance of the CAT-TPC was evaluated using a collimated a-particle source.A time resolution of less than 20 ns and a position resolution of less than 0.2 mm were observed along the electron drift direction.Threedimensional images of incident trajectories and scattering events can be clearly reconstructed under an angular resolution of approximately 0.45 degree.

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.

Prototype of the readout electronics for the RICH PID detector in the STCF

The ring imaging Cherenkov(RICH) detector for particle identification(PID) is being evaluated for the future super tau-charm facility(STCF) complex. In this work, the prototype readout electronics for the RICH PID detector is designed. The prototype RICH PID detector is based on a thick gas electron multiplier combined with a micromegas detector for Cherenkov light detection. Considering that there will be a large number(~ 690,000) of detector channels in future RICH detector, the readout electronics faces many challenges to precisely measuring time and charge information, such as reducing the noise,increasing density, and improving precision. The requirements of the readout electronics are explored, the downselection of the ASICs is made and thus a prototype readout electronics is designed and implemented. Tests are also conducted to evaluate the performance of the prototype readout electronics, and the results indicate that the time resolution is better than ~ 1 ns(RMS) when the input charge is greater than ~ 12 fC based on the APV25chip, while the time resolution is better than ~ 1 ns(RMS) at an input charge of over ~ 48 fC based on the AGET and STCF ASIC chips, and the equivalent noise charge is better than ~ 0.5 fC(RMS) @ 20 pF based on the three ASICs. The test results indicate that the prototype readout electronics design meets the requirement of the future RICH PID detector and thus provides a reference for future engineering.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Design of a Low-Noise Front-End Readout CSP-Shaper System for CZT Detectors

This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

Design of fast adaptive readout system for wire scanners

A new wide-range fast readout system capable of adaptive identification is designed for wire scanners,which are used to measure beam profiles and emittance.This system is capable of handling varying current signals with Gaussian distributions and current pulses up to 1000 counts/s, as well as an input current range of 1 n A–1 m A. When tested, the resolution was found to exceed 3.68% for full scale, the nonlinearity was found to be less than 0.11%, and the measurement sensibility was found to be less than 5 p A. We believe that the system will play a crucial role in improving the measurement accuracy of beam diagnosis and the efficiency of accelerator operation,as well as decreasing the time required for beam tuning.This system was applied to the beam diagnosis of an injector II prototype for an accelerator-driven subcritical system and produced excellent measurement results. A description of the adaptive fast readout system for wire scanners is presented in this paper.