Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.

New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications

A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage capacity is 3 × 108 electrons. The function and performance of the proposed readout circuit have been verified by experimental results.

Ultra-low Power CMOS Front-End Readout ASIC for Portable Digital Radiation Detector

An ultra-low power complementary metal-oxide-semiconductor （CMOS） front-end readout ASIC was developed for a portable digital radiation detector. The ASIC having a charge sensitive amplifier and a semi-Gaussian pulse-shaper was produced using the CSMC 0.5 μm DPDM process. The ENC noise of 363 e at 0 pF with a noise slope of 23 e/pF complies with the stringent low noise requirements. The peaking time was 250 ns at a 100 mV/fC conversion gain （detector capacitance is 20 pF）. By operating this frontend readout ASIC in the weak inversion region, the ultra-low power dissipation is only 0.1 mW/channel （3.0 V） Simulations and test results suggest that this design gives lower power consumption than the front-end readout ASICs working in the strong inversion and is appropriate for the portable digital radiation detectors.

A 97 dB dynamic range CSA-based readout circuit with analog temperature compensation for MEMS capacitive sensors

Abstract： This paper presents a charge-sensitive-amplifier （CSA） based readout circuit for capacitive microelectro-mechanical-system （MEMS） sensors. A continuous-time （CT） readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits. An operational trans-conductance amplifier （OTA） structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal. An analog temperature compensation method is proposed, which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity. The chip is designed and implemented in a 0.35μm CMOS process and is 2.1 × 2.1 mm2 in area. The measurement shows that the readout circuit achieves 0.9 aF/√H capacitive resolution, 97 dB dynamic range in 100 Hz signal bandwidth, and 0.8 mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.

Design of current mirror integration ROIC for snapshot mode operation

Current mirror integration（CMI） read out integrated circuit（ROIC） topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30×30μm^2 pixel size, 4×4 array size, variable frame rate, 5 Me charga pixel per second（Mpps）.Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6 MUMC180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.