A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Exponential sine chaotification model for enhancing chaos and its hardware implementation

Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems weakens chaos-based practical applications. Designing chaotic maps with high complexity is attractive. This paper proposes the exponential sine chaotification model(ESCM), a method of using the exponential sine function as a nonlinear transform model, to enhance the complexity of chaotic maps. To verify the performance of the ESCM, we firstly demonstrated it through theoretical analysis. Then, to exhibit the high efficiency and usability of ESCM, we applied ESCM to one-dimensional(1D) and multidimensional(MD) chaotic systems. The effects were examined by the Lyapunov exponent and it was found that enhanced chaotic maps have much more complicated dynamic behaviors compared to their originals. To validate the simplicity of ESCM in hardware implementation, we simulated three enhanced chaotic maps using a digital signal processor(DSP). To explore the ESCM in practical application, we applied ESCM to image encryption. The results verified that the ESCM can make previous chaos maps competitive for usage in image encryption.

Quasi-cyclic Random Projection Code and Hardware Implementation

Random Projection Code (RPC) is a mechanism that combines channel coding and modulation together and realizes rate adaptation in the receiving end. Random projection code’s mapping matrix has significant influences on decoding performance as well as hardware implementation complexity. To reduce hardware implementation complexity, we design a quasi-cyclic mapping matrix for RPC codes. Compared with other construction approaches, our design gets rid of data filter component, thus reducing chip area 7284.95 um2, and power consumption 331.46 uW in 0.13 um fabrication. Our simulation results show that our method does not cause any performance loss and even gets 0.2 dB to 0.5 dB gain at BER 10-4.

Features of hardware implementation of quasi-continuous observation devices with discrete receivers

This article proposes an approach to the formalization of tasks and conditions for the hardware implementation of quasi-continuous observation devices with discrete receivers in remote sensing systems.Observation devices with a matrix are used in medicine,ecology,aerospace photography,and geodesy,among other fields.In the discrete receivers,the sampling of an image in the matrix receiver into pixels leads to a decrease in the spatial information of the object.In a greater extent,these disadvantages can be avoided by using photosensitive matrix with a regularly changing(controlled)density of elementary receivers-matrix(RCDOER-matrix).Currently,there is no substantiation of the tasks and conditions for the hardware implementation of RCDOER-matrix.The algorithmic formation of a quasi-continuous image of observation devices with the RCDOER-matrix is proposed.The algorithm used a formal pixel-by-pixel description of the signals in the image.This algorithm formalizes the requirements for creating a photosensitive RCDOER-matrix of a certain size,as well as for changing the mechanism for forming and saving a frame with observation results.The application of the developed method will allow multiplying the pixel size of the image relative to the pixel size of the RCDOER-matrix.Developed algorithms for RCDOER-matrix are supplemented by formalizing the tasks that arise when creating prototypes.In addition,the conditions for hardware implementation are proposed,which ensure the completeness of registration of the observation picture,and allow avoiding excessive pixel measurements.Thus,the results of the research carried out approximate the practical application of RCDOER-matrix.

Energy Detector with Baseband Sampling for Cognitive Radio: Real-Time Implementation

Cognitive radio (CR) is a technology that provides a promising new way to improve the efficiency of the use of the electromagnetic spectrum that available. Spectrum sensing helps in the detection of spectrum holes (unused channels of the band), and instantly move into vacant channels while avoiding occupied ones. An energy detector with baseband sampling for CR is presented with mathematical analyses for an additive white Gaussian noise (AWGN) channels. A brief overview of the energy detection based spectrum sensing for CR technology is introduced. Practical implementation issues on Texas Instruments TMS320C6713 floating point DSP board are presented. Novelties of this work came from a derivation of probability of detection and probability of false alarm for the baseband energy detector without including the sampling theorems and the associated approximation.

FPGA Implementation of Extended Kalman Filter for Parameters Estimation of Railway Wheelset

It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars.In this paper,the development of simulation model of extended Kalman filter(EKF)in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track.Due to concurrent in nature,the Xilinx®System-on-Chip Zynq Field Programmable Gate Array(FPGA)device is chosen to check the onboard estimation ofwheel-rail interaction parameters by using the National Instruments(NI)myRIO®development board.The NImyRIO®development board is flexible to deal with nonlinearities,uncertain changes,and fastchanging dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation.The simulated dataset of the railway nonlinear wheelsetmodel is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle.The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA.The obtained simulation results are aligned with the simulation results obtained through MATLAB.To the best of our knowledge,this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification.The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.

List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb0_(3) process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

High Speed Digital Oscillator Implementations Based on Advanced Arithmetic and Architecture Techniques

The advances of digital arithmetic techniques permit computer designers to implement high speed application specific chips. The currently produced digital circuits have demonstrated high performance in terms of several criteria, such as, high clock rate, short input/output delay, small silicon area, and low power dissipation. In this paper, we implement several sinusoidal generation methods to optimize their performance and output using advanced digital arithmetic techniques. In this paper, the implementations of advanced digital oscillator structures with and without pipelining are proposed. The synthesis results of the implementation with pipelining have proven that it is superior to other sinusoidal generation methods in terms of the maximum frequency and signal resolution. Hence, this method is used in the design of the proposed digital oscillator chip.

A Novel Medium Access Control Protocol for Real-Time Wireless Communications in Industrial Automation

In this paper, a novel Medium Access Control (MAC) protocol for industrial Wireless Local Area Networks (WLANs) is proposed and studied. The main challenge in industry automation systems is the ultra-low network latency with a target upper bound in the order of 1 ms while maintaining high network reliability and availability. The novelty of the proposed wireless MAC protocol resides in its similar latency performance as its counterpart in wired industrial LAN. First, the functional design of the MAC protocol is introduced. Then its performance results gained from hardware implementation (SystemC and VHDL) on an FPGA platform are presented. Finally, a real-time communication module which achieves the ultra-low latency required in industrial automation is described.

Two Methods of AES Implementation Based on CPLD/FPGA

This paper describes two single-chip——complex programmable logic devices/field programmable gate arrays(CPLD/FPGA)——implementations of the new advanced encryption standard (AES) algorithm based on the basic iteration architecture (design [A]) and the hybrid pipelining architecture (design [B]). Design [A] is an encryption-and-decryption implementation based on the basic iteration architecture. This design not only supports 128-bit, 192-bit, 256-bit keys, but saves hardware resources because of the iteration architecture and sharing technology. Design [B] is a method of the 2×2 hybrid pipelining architecture. Based on the AES interleaved mode of operation, the design successfully accomplishes the algorithm, which operates in the feedback mode (cipher block chaining). It not only guarantees security of encryption/decryption, but obtains high data throughput of 1.05 Gb/s. The two designs have been realized on Aitera′s EP20k300EBC652-1 devices.

Dilithium算法的FPGA高效扩展性优化

为提高Dilithium在实际应用中的运行效率,提出了一种Dilithium算法的现场可编程门阵列(Field Programmable Gate Array,FPGA)高效扩展性优化实现。具体在以下几个方面进行优化:将KOA(Karatsuba-Offman-Algorithm)算法与快速模约减算法相结合,构成快速模乘单元,优化数论转换(Number TheoreticTransform,NTT)实现的大量多项式乘法;采用多RAM(Random Access Memory)存取参与运算的多项式系数,根据Dilithium算法的特点,设计了一种多项式系数读取策略,以快速、正确地读取RAM中的多项式系数。针对方案中的采样和散列工作,分析了SHAKE算法系列的特点,设计了一种低延迟可扩展的Keccak硬件架构,使得其能够根据输入信号的不同执行不同的SHAKE算法。实验结果表明,所提方案在频率方面相比其他方案提升了60.7%~131.9%,兼顾硬件的资源消耗和执行效率。

差速轮式移动机器人控制系统设计

差速轮式移动机器人在现代自动化和智能化领域中扮演着愈发关键的角色。为满足不断增长的自动化需求,该文设计一款用于室外环境的差速轮式移动机器人控制系统,该系统综合考虑电源系统、驱动系统、传感器系统、人机交互系统和通信系统的设计,以支持运动控制、环境感知、定位、人机交互和远程通信等核心功能,通过软硬件设计,最终实现可靠稳定的差速轮式移动机器人控制系统。经过测试,各项功能正常,实现预期目标,可为机器人技术进一步发展和应用奠定坚实的基础。

CRYSTALS-Kyber算法的IP核设计与验证方案研究

随着量子计算机的不断发展,现有的公钥密码算法随时面临着失效的危机。而抗量子密码(PQC)算法的出现,使得这一危机得到化解。与此同时,CRYSTALS-Kyber算法由于其安全性高、速度快等优点在美国国家标准与技术研究院(NIST)标准化算法中脱颖而出。为提高硬件实现的效率及安全性,提出了一种基于CRYSTALS-Kyber算法的知识产权(IP)核设计与验证的方案。介绍了该系统的硬件实现方法及其中包含的3个模块,密钥生成模块、加密模块和解密模块,研究了实现IP核的关键单元数论变换(NTT)、高级可扩展接口(AXI)以及仿真验证的具体方案,并对总体方案进行了可行性分析。

一种应用于椭圆曲线密码的双域模加减运算的优化设计

椭圆曲线密码算法由于其安全特性被广泛应用于各种领域,当前支持多协议和多域的ECC算法成为研究的热点。围绕素数域和二元域下的ECC算法展开研究,对双域模加减运算进行了优化设计。针对素数域模加减运算中加法器计算延时较大的问题,设计素数域的模加和模减运算使用同一个运算通路,使用进位保留加法器和加法器组合对电路结构进行优化,缩短素数域模加减运算时间。

基于比特重组快速模约简的高面积效率椭圆曲线标量乘法器设计

针对现有椭圆曲线密码标量乘法器难以兼顾灵活性和面积效率的问题,该文设计了一种基于比特重组快速模约简的高面积效率标量乘法器。首先,根据椭圆曲线标量乘的运算特点,设计了一种可实现乘法和模逆两种运算的硬件复用运算单元以提高硬件资源使用率,并采用Karatsuba-Ofman算法提高计算性能。其次,设计了基于比特重组的快速模约简算法,并实现了支持secp256k1, secp256r1和SCA-256(SM2标准推荐曲线)快速模约简计算的硬件架构。最后,对点加和倍点的模运算操作调度进行了优化,提高乘法与快速模约简的利用率,降低了标量乘计算所需的周期数量。所设计的标量乘法器在55 nm CMOS工艺下需要275 k个等效门,标量乘运算速度为48 309次/s,面积时间积达到5.7。

基于流水线的RSA加密算法硬件实现

针对硬件实现高位RSA加密算法成本比较高的问题,在传统的基4蒙哥马利(Montgomery)算法上进行改进。首先引入CSA加法器快速完成大数的加法计算;然后在后处理上做优化,以减少每次蒙哥马利计算的大数个数;最后在计算RSA加密算法时加入了流水线,在并行执行RSA加密的条件下降低硬件资源的使用。在Xilinx XC7K410T系列的FPGA开发板上的实验结果表明,在保证加密速率的前提下,改进的RSA加密算法结构使用的硬件资源是原来并行结构的1/2,而且可以在更高的频率下工作。

机载超轻量化卷积神经网络加速器设计

卷积神经网络庞大的权重参数和复杂的网络层结构,使其计算复杂度过高,所需的计算资源和存储资源也随着网络层数的增加而快速增长,难以在资源和功耗有严苛要求的机载嵌入式计算系统中部署,制约了机载嵌入式计算系统朝着高智能化发展。针对资源受限的机载嵌入式计算系统对超轻量化智能计算的需求,提出一套全流程的卷积神经网络模型优化加速方法,在对算法模型进行超轻量化处理后,通过组合加速算子搭建卷积神经网络加速器,并基于FPGA开展网络模型推理过程的功能验证。结果证明:本文搭建的加速器能够显著降低硬件资源占用率,获得良好的算法加速比,对机载嵌入式智能计算系统设计具有重要意义。

卫星图像处理算法研究及其硬件实现

随着航天技术的快速发展,其空间遥感技术带来的数据逐渐扩增,传统存储器的处理办法无法有效匹配无损图像处理的存储需要,卫星的信息容量也导致了传输瓶颈的出现。要实现其卫星图像的有效处理,必须对卫星图像的算法和硬件进行重新构造。

Flatness predictive model based on T-S cloud reasoning network implemented by DSP

The accuracy of present flatness predictive method is limited and it just belongs to software simulation. In order to improve it, a novel flatness predictive model via T-S cloud reasoning network implemented by digital signal processor(DSP) is proposed. First, the combination of genetic algorithm(GA) and simulated annealing algorithm(SAA) is put forward, called GA-SA algorithm, which can make full use of the global search ability of GA and local search ability of SA. Later, based on T-S cloud reasoning neural network, flatness predictive model is designed in DSP. And it is applied to 900 HC reversible cold rolling mill. Experimental results demonstrate that the flatness predictive model via T-S cloud reasoning network can run on the hardware DSP TMS320 F2812 with high accuracy and robustness by using GA-SA algorithm to optimize the model parameter.