Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier （DTSCR） is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing （TLP） test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor （CMOS） process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

Design of a novel high holding voltage LVTSCR with embedded clamping diode

In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier(LVTSCR), a novel LVTSCR with embedded clamping diode(DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+implant region and the n+bridge, which helps to improve the holding voltage and decrease the snapback region.The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse(TLP)tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.

Power supply for generating frequency-variable resonant magnetic perturbations on the J-TEXT tokamak

To further research the response of the tearing mode（TM） to dynamic resonant magnetic perturbation（DRMP） on the J-TEXT tokamak, a modified series resonant inverter power supply（MSRIPS） with a function of discrete variable frequency is designed for DRMP coils in this study. The MSRIPS is an AC–DC–AC converter, including a phase-controlled rectifier, an LC filter, an insulated gate bipolar transistor（IGBT） full bridge, a matching transformer, three resonant capacitors with different capacitance values, and three corresponding silicon controlled rectifier（SCR） switches. The function of discrete variable frequency is realized by switching over different resonant capacitors with corresponding SCR switches while matching the corresponding driving frequency of the IGBT full bridge. A detailed switching strategy of the SCR switch is put forward to obtain sinusoidal current waveform and realize current waveform smooth transition during frequency conversion. In addition, a resistor and thyristor bleeder is designed to protect the SCR switch from overvoltage. Manufacturing of the MSRIPS is completed, and the MSRIPS equipment can output current with an amplitude of 1.5 kA when its working frequency jumps among different frequencies. Moreover, the current waveform is sinusoidal and can smoothly transition during frequency conversion. Furthermore, the transition time when the current amplitude rises from zero to a steady state is less than 2 ms during frequency conversion. By using the MSRIPS, the expected discrete variable frequency DRMP is generated, and the phenomenon of the TM being locked to the discrete variable frequency DRMP is observed on the J-TEXT tokamak.

Multifunction Plasma Arc Equipment

A new type of plasma arc equipment with four functions including plasma arc welding, cutting, spraying and a surfacing process was designed and manufactured. To obtain good processing stability and multifunction integration, a silicon controlled rectifier (SCR), and the programmable controller (PC) were introduced. The operation of this new machine shows that it has the advantage of simple circuit design, flexible control pattern, low fault rate and easy maintenance.

Design of novel DDSCR with embedded PNP structure for ESD protection

A novel dual-directional silicon controlled rectifier（DDSCR） device with embedded PNP structure（DDSCR-PNP） is proposed for electrostatic discharge（ESD） protection, which has greatly reduced latch-up risk owing to the improved holding voltage（V_h/. Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP（PNP_2）. Then, experimental devices are fabricated in a 0.35 m bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the V_h of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width.However, the reduced leakage current（I_L/ of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12 m. Finally, the factors influencing V_h and I_L are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase V_h and decrease I_L. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased I_L. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.

A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection

The turn-on speed of electrostatic discharge （ESD） protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device （DTSCR） can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors. Using the variation lateral base doping （VLBD） structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure （VLBD_DTSCR） is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n-p-n and p--n-p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.

Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

The trigger voltage walkin effect has been investigated by designing two different laterally diffused metal-oxide-semiconductor （LDMOS） transistors with an embedded silicon controlled rectifier （SCR）. By inserting a P＋ implant region along the outer and the inner boundary of the N＋ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5/zm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse （TLP） and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

A novel ESD protection structure for output pads

Electro-static discharge （ESD） is always a serious threat to integrated circuits. To achieve higher robustness and a smaller die area at the same time, a novel protection structure for the output pad is proposed. The complementary SCR devices in this structure can protect not only the output under positive or negative stresses versus VDD or Vss, respectively, but also the power rails at the cost of almost no extra area. The robustness of the proposed structure is about three times higher than the conventional four-finger GGNMOS/GDPMOS structure in the same area condition.