大规模安全约束机组组合(security constrained unit commitment,SCUC)问题的混合整数线性规划(mixed integer linear programming,MILP)模型因其高维、非凸的特点导致求解困难,尤其在考虑故障态安全约束后模型规模骤增,MILP算法常遇到...大规模安全约束机组组合(security constrained unit commitment,SCUC)问题的混合整数线性规划(mixed integer linear programming,MILP)模型因其高维、非凸的特点导致求解困难,尤其在考虑故障态安全约束后模型规模骤增,MILP算法常遇到收敛间隙下降瓶颈问题。为满足现货市场出清对SCUC问题求解时间的要求,提出了基于热启动的快速求解方法,从待求模型的一个可行解出发,根据节点边际电价和机组收益分析进行整数变量固定,同时削减无约束力的安全约束,以缩减模型规模,加快收敛进程。仿真结果表明:所提方法能够大幅缩减SCUC模型规模,尤其对于考虑故障态安全约束的大规模SCUC问题,能有效克服收敛间隙下降瓶颈问题,求解效率提高特别显著。展开更多
For neural networks(NNs)with rectified linear unit(ReLU)or binary activation functions,we show that their training can be accomplished in a reduced parameter space.Specifically,the weights in each neuron can be traine...For neural networks(NNs)with rectified linear unit(ReLU)or binary activation functions,we show that their training can be accomplished in a reduced parameter space.Specifically,the weights in each neuron can be trained on the unit sphere,as opposed to the entire space,and the threshold can be trained in a bounded interval,as opposed to the real line.We show that the NNs in the reduced parameter space are mathematically equivalent to the standard NNs with parameters in the whole space.The reduced parameter space shall facilitate the optimization procedure for the network training,as the search space becomes(much)smaller.We demonstrate the improved training performance using numerical examples.展开更多
In earlier papers [1]-[4], it was shown that the consistency of the concept of time with motion requires time and distance to be of the same dimension, and thus measured by the same unit. The arising reduced system of...In earlier papers [1]-[4], it was shown that the consistency of the concept of time with motion requires time and distance to be of the same dimension, and thus measured by the same unit. The arising reduced system of units revealed that mass and energy were only different facets of one entity, and resulted in the well-known mass-energy equivalence formula as a natural consequence. The physical space can be identified with any inertial frame, but when it comes to comparing the results of measurements in two frames, or more, only one frame, say S, can be taken stationary and identified with the physical space, whereas all other inertial frames are moving relative to S. The equivalence of inertial frames as sites of one physical world implies that an intrinsic units system of length, time, mass and charge should be defined in terms of basic constituent physical blocks that have the same identity in all inertial frames. A basic feature of the universal space and time theory (UST) is that the same one time prevails in all inertial frames. The scaling transformations (STs) that relate the geometric distances in two frames, S (s) when chosen the stationary frame, are derived, and applied to explain the Doppler’s effect. The time distance between a moving object in S and an observer depends on its state of motion;and the Euclidean form of the STs is employed to explain arrival of some meta-stable at the earth’s surface despite its short lifetime. The quantitative predicted Doppler’s effect, which is in a striking agreement with the Ives-Stilwell experimental results, coincides with the relativistic prediction for longitudinal motion, but yet predicts a complete absence of a transverse effect at a right angle. In coming parts of this work it will be shown that the UST explains elaborately the drag effect, stellar aberration, and produces naturally the relativistic mechanics. The UST will also be completed through deriving the scaling transformations of the second type, by which the null results of Michelson and Morley experiment, Michelson and Gale experiment, and the Sagnac effect are explained. The current work and our intended future works in UST are new versions containing basic conceptions and visions that didn’t appear in earlier versions [1]-[6].展开更多
A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many po...A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.展开更多
文摘大规模安全约束机组组合(security constrained unit commitment,SCUC)问题的混合整数线性规划(mixed integer linear programming,MILP)模型因其高维、非凸的特点导致求解困难,尤其在考虑故障态安全约束后模型规模骤增,MILP算法常遇到收敛间隙下降瓶颈问题。为满足现货市场出清对SCUC问题求解时间的要求,提出了基于热启动的快速求解方法,从待求模型的一个可行解出发,根据节点边际电价和机组收益分析进行整数变量固定,同时削减无约束力的安全约束,以缩减模型规模,加快收敛进程。仿真结果表明:所提方法能够大幅缩减SCUC模型规模,尤其对于考虑故障态安全约束的大规模SCUC问题,能有效克服收敛间隙下降瓶颈问题,求解效率提高特别显著。
文摘For neural networks(NNs)with rectified linear unit(ReLU)or binary activation functions,we show that their training can be accomplished in a reduced parameter space.Specifically,the weights in each neuron can be trained on the unit sphere,as opposed to the entire space,and the threshold can be trained in a bounded interval,as opposed to the real line.We show that the NNs in the reduced parameter space are mathematically equivalent to the standard NNs with parameters in the whole space.The reduced parameter space shall facilitate the optimization procedure for the network training,as the search space becomes(much)smaller.We demonstrate the improved training performance using numerical examples.
文摘In earlier papers [1]-[4], it was shown that the consistency of the concept of time with motion requires time and distance to be of the same dimension, and thus measured by the same unit. The arising reduced system of units revealed that mass and energy were only different facets of one entity, and resulted in the well-known mass-energy equivalence formula as a natural consequence. The physical space can be identified with any inertial frame, but when it comes to comparing the results of measurements in two frames, or more, only one frame, say S, can be taken stationary and identified with the physical space, whereas all other inertial frames are moving relative to S. The equivalence of inertial frames as sites of one physical world implies that an intrinsic units system of length, time, mass and charge should be defined in terms of basic constituent physical blocks that have the same identity in all inertial frames. A basic feature of the universal space and time theory (UST) is that the same one time prevails in all inertial frames. The scaling transformations (STs) that relate the geometric distances in two frames, S (s) when chosen the stationary frame, are derived, and applied to explain the Doppler’s effect. The time distance between a moving object in S and an observer depends on its state of motion;and the Euclidean form of the STs is employed to explain arrival of some meta-stable at the earth’s surface despite its short lifetime. The quantitative predicted Doppler’s effect, which is in a striking agreement with the Ives-Stilwell experimental results, coincides with the relativistic prediction for longitudinal motion, but yet predicts a complete absence of a transverse effect at a right angle. In coming parts of this work it will be shown that the UST explains elaborately the drag effect, stellar aberration, and produces naturally the relativistic mechanics. The UST will also be completed through deriving the scaling transformations of the second type, by which the null results of Michelson and Morley experiment, Michelson and Gale experiment, and the Sagnac effect are explained. The current work and our intended future works in UST are new versions containing basic conceptions and visions that didn’t appear in earlier versions [1]-[6].
文摘A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.
