Micro-satellite cluster enables a whole new class of missions for communications, remote sensing, and scientific research for both civilian and military purposes. Synchronizing the time of the satellites in a cluster ...Micro-satellite cluster enables a whole new class of missions for communications, remote sensing, and scientific research for both civilian and military purposes. Synchronizing the time of the satellites in a cluster is important for both cluster sensing capabilities and its autonomous operating. However, the existing time synchronization methods are not suitable for microsatellite cluster, because it requires too many human interventions and occupies too much ground control resource. Although, data post-process may realize the equivalent time synchronization, it requires processing time and powerful computing ability on the ground, which cannot be implemented by cluster itself. In order to autonomously establish and maintain the time benchmark in a cluster, we propose a compact time difference compensation system（TDCS）, which is a kind of time control loop that dynamically adjusts the satellite reference frequency according to the time difference. Consequently, the time synchronization in the cluster can be autonomously achieved on-orbit by synchronizing the clock of other satellites to a chosen one＇s. The experimental result shows that the standard deviation of time synchronization is about 102 ps when the carrier to noise ratio（CNR） is 95 d BHz, and the standard deviation of corresponding frequency difference is approximately0.36 Hz.展开更多
A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs...A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.展开更多
基金supported by the National Natural Science Foundation of China(61401389)the Joint Fund of the Ministry of Education of China(6141A02033310)
文摘Micro-satellite cluster enables a whole new class of missions for communications, remote sensing, and scientific research for both civilian and military purposes. Synchronizing the time of the satellites in a cluster is important for both cluster sensing capabilities and its autonomous operating. However, the existing time synchronization methods are not suitable for microsatellite cluster, because it requires too many human interventions and occupies too much ground control resource. Although, data post-process may realize the equivalent time synchronization, it requires processing time and powerful computing ability on the ground, which cannot be implemented by cluster itself. In order to autonomously establish and maintain the time benchmark in a cluster, we propose a compact time difference compensation system（TDCS）, which is a kind of time control loop that dynamically adjusts the satellite reference frequency according to the time difference. Consequently, the time synchronization in the cluster can be autonomously achieved on-orbit by synchronizing the clock of other satellites to a chosen one＇s. The experimental result shows that the standard deviation of time synchronization is about 102 ps when the carrier to noise ratio（CNR） is 95 d BHz, and the standard deviation of corresponding frequency difference is approximately0.36 Hz.
基金Project supported by the National Natural Science Foundation of China(No.61176029)the National Twelve-Five Project(No.513***)
文摘A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.
