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Dielectric Analysis of Dynamic Fouling Behavior on Surface of Polyethersulfone Composite Ultrafiltration Membrane
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作者 罗明良 温庆志 +1 位作者 刘佳林 刘洪见 《Chinese Journal of Chemical Physics》 SCIE CAS CSCD 2010年第2期241-248,I0002,共9页
A dielectric analysis model for the fouling layer on the polyethersulfone composite ultrafiltration (UF) membrane and solution system, which consists of the solution, concentration polarization layer (CPL), and ca... A dielectric analysis model for the fouling layer on the polyethersulfone composite ultrafiltration (UF) membrane and solution system, which consists of the solution, concentration polarization layer (CPL), and cake layer, was established by virtue of the interfacial polarization and the electrostatic field theory. The effect of some important parameters, such as the depth, conductivity of CPL, and cake layer, on the dielectric spectroscopy (or dielectric relaxation properties) of the UF system was discussed by the parameter sensitivity analysis and the dielectric measurement. The simulations indicate that the CPL can be created rapidly and the cake layer formation is the dynamic balance process of growth and erosion in the process of UF. The key factor affecting on the dielectric spectrum of UF system is the electrical properties of the CPL and the cake layer. In comparison to the results of dielectric measurement, the simulations indicate that the model proposed in this work is valid and reliable to some degree for describing and explaining the dielectric relaxation phenomenon in UF system. It is very important to further understand the fouling behavior of membrane surface and optimize the controlling techniques of membrane fouling in the process of UF. 展开更多
关键词 Interfacial polarization Cake layer Dynamic fouling Ultrafiltration Dielec-tric relaxation
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β-distribution for Reynolds stress and turbulent heat flux in relaxation turbulent boundary layer of compression ramp
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作者 YanChao Hu WeiTao Bi +1 位作者 ShiYao Li ZhenSu She 《Science China(Physics,Mechanics & Astronomy)》 SCIE EI CAS CSCD 2017年第12期36-44,共9页
A challenge in the study of turbulent boundary layers(TBLs) is to understand the non-equilibrium relaxation process after separation and reattachment due to shock-wave/boundary-layer interaction. The classical boundar... A challenge in the study of turbulent boundary layers(TBLs) is to understand the non-equilibrium relaxation process after separation and reattachment due to shock-wave/boundary-layer interaction. The classical boundary layer theory cannot deal with the strong adverse pressure gradient, and hence, the computational modeling of this process remains inaccurate. Here, we report the direct numerical simulation results of the relaxation TBL behind a compression ramp, which reveal the presence of intense large-scale eddies, with significantly enhanced Reynolds stress and turbulent heat flux. A crucial finding is that the wall-normal profiles of the excess Reynolds stress and turbulent heat flux obey a β-distribution, which is a product of two power laws with respect to the wall-normal distances from the wall and from the boundary layer edge. In addition, the streamwise decays of the excess Reynolds stress and turbulent heat flux also exhibit power laws with respect to the streamwise distance from the corner of the compression ramp. These results suggest that the relaxation TBL obeys the dilation symmetry, which is a specific form of self-organization in this complex non-equilibrium flow. The β-distribution yields important hints for the development of a turbulence model. 展开更多
关键词 compression ramp relaxation turbulent boundary layer Reynolds stress β-distribution symmetry
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A strained Si-channel NMOSFET with low field mobility enhancement of about 140% using a SiGe virtual substrate 被引量:2
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作者 崔伟 唐昭焕 +6 位作者 谭开洲 张静 钟怡 胡辉勇 徐世六 李平 胡刚毅 《Journal of Semiconductors》 EI CAS CSCD 2012年第9期65-68,共4页
A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe l... A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe layer and forming a p-well by multiple implantation technology, a surface strained Si-channel NMOSFET was fabricated, of which the low field mobility was enhanced by 140%, compared with the bulk-Si control device. Strained NMOSFET and PMOSFET were used to fabricate a strained CMOS inverter based on a SiGe virtual substrate. Test results indicated that the strained CMOS converter had a drain leakage current much lower than the Si devices, and the device exhibited wonderful on/off-state voltage transmission characteristics. 展开更多
关键词 CMOS inverter strained Si mobility enhancement SiGe virtual substrate relaxed layer
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